[Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=617

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Cesar when it comes to it, here's how to skip over src and dest elements
that have predication bits zero:

            while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
                print ("      skip", bin(1<<srcstep))
                srcstep += 1

            # same for dststep
            while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
                print ("      skip", bin(1<<dststep))
                dststep += 1

it's actually very simple, hilarious thing is, this is pretty much the exact
same behaviour as "set before first" predicate mask instruction.

so that would go in the... err... issue FSM, before triggering execute.

the only thing to watch out for is that this changes the srcstep and
dststep used in PowerDecoder2 (svstate) so you have to give PowerDecoder2
a chance to settle after skipping srcstep and dststep

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/isa/caller.py;h=23c1c5aeaed589bbed957d4ea2d86153295ada19;hb=HEAD#l946

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