From bugzilla-daemon at libre-soc.org Mon Mar 1 18:48:16 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 01 Mar 2021 18:48:16 +0000 Subject: [Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=517 --- Comment #71 from Luke Kenneth Casson Leighton --- (In reply to Cole Poirier from comment #70) > > suggest replacing terse word "Attach" with "Attach M2F" or F2F as > > appropriate and define that in brackets directly above. > > I have made the requested changes. looks great. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 1 18:51:10 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 01 Mar 2021 18:51:10 +0000 Subject: [Libre-soc-bugs] [Bug 607] unnecessary code added related to MMU in PowerDecoder2 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=607 Tobias Platen changed: What |Removed |Added ---------------------------------------------------------------------------- Status|RESOLVED |CONFIRMED Resolution|FIXED |--- --- Comment #4 from Tobias Platen --- In src/soc/simple/core.py I added this line: self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"] after having found out using GTKWave that the insn_type for mmu0 is OP_INVALID in my unit test where is use "mtspr 18, 1". The correct insn_type for DSISR DAR SVSRR0 and PIDR is passed to the wrong function unit instead. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 1 18:51:57 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 01 Mar 2021 18:51:57 +0000 Subject: [Libre-soc-bugs] [Bug 605] Extend ECP5_FPGA wiki page with JTAG testing/boot procedure for Libre-SOC test chip In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=605 --- Comment #1 from Luke Kenneth Casson Leighton --- (In reply to Cole Poirier from comment #0) > Once #517 JTAG STLINKv2 to FPGA connection guide wiki is complete: > > * lkcl to outline Libre-SOC test chip boot via jtag procedure for testing on > FPGA before the test ASIC is taped-out in the README is the version for sim.py https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/README.txt;h=2cab663850af1c530d852f948bf79e5795bb7e2a;hb=HEAD the FPGA and ASIC variant is near-identical. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 1 18:58:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 01 Mar 2021 18:58:39 +0000 Subject: [Libre-soc-bugs] [Bug 605] Extend ECP5_FPGA wiki page with JTAG testing/boot procedure for Libre-SOC test chip In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=605 --- Comment #2 from Luke Kenneth Casson Leighton --- also this can be run (it uploads bytes 0x1 and 0x2 presently, needs to be given a filename) https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/firmware_upload.py;hb=HEAD it can be used to talk jtagremote protocol (via openocd) so that it actually connects directly to the FPGA (or ASIC) and uploads firmware to it. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 1 19:41:14 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 01 Mar 2021 19:41:14 +0000 Subject: [Libre-soc-bugs] [Bug 607] unnecessary code added related to MMU in PowerDecoder2 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=607 --- Comment #5 from Luke Kenneth Casson Leighton --- (In reply to Tobias Platen from comment #4) > In src/soc/simple/core.py I added this line: > self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"] ok that will need a comment, cross-reference this bugreport as well special-case hacks like that we need to pay attention to. then also cross-reference it in PowerDecoderSubset as well, that mmu_spr_dec is set up in simple/core.py what we don't need is surprises when people go "where does mmu0_spr_dec come from, it's not in the constructor, wtf??" > after having found out using GTKWave that the insn_type for mmu0 is > OP_INVALID in my unit test where is use "mtspr 18, 1". The correct insn_type > for DSISR DAR SVSRR0 and PIDR is passed to the wrong function unit instead. yyeah this is because of the subset decoding. there may be more that needs doing, here. note i've just pushed this: commit f5549bf43d740610a5980b5930241ff37641bdd6 (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton Date: Mon Mar 1 19:35:31 2021 +0000 Revert "fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2" -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 1 21:10:10 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 01 Mar 2021 21:10:10 +0000 Subject: [Libre-soc-bugs] [Bug 607] unnecessary code added related to MMU in PowerDecoder2 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=607 --- Comment #6 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;h=6b3530813943dd37a07bc68d42c4c4cbaf7deac2;hb=HEAD#l774 rright. ok. what this is doing is asking BOTH the SPR *AND* the MMU pipelines to process the MTMSR operation. clearly this is disastrous because there will be two FUs fighting for the register file amongst other things. try moving it to PowerDecoder2, removong mmu_spr_dec and simply "overriding" the fn_unit etc. with m.If((fn_unit == Function.SPR) & OP_MTMSR & DSR etc etc)) comb += self.do_copy("fn_unit", Function.MMU) this *really* should be enough to get the operation redirected to the correct FU Decoder. ohh i know what needs to be done. there is a filter which selects the rows of CSV files. because the CSV file says "this is for SPR pipe" it is getting filtered out. let me find the location. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 1 21:15:23 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 01 Mar 2021 21:15:23 +0000 Subject: [Libre-soc-bugs] [Bug 607] unnecessary code added related to MMU in PowerDecoder2 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=607 --- Comment #7 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;h=6b3530813943dd37a07bc68d42c4c4cbaf7deac2;hb=HEAD#l715 found it. urr this is a nuisance. i think the solution here is to modify the CSV files or perhaps even add special sub-processing entries for the SPR field. have to think -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Mar 2 18:10:57 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 02 Mar 2021 18:10:57 +0000 Subject: [Libre-soc-bugs] [Bug 607] unnecessary code added related to MMU in PowerDecoder2 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=607 --- Comment #8 from Luke Kenneth Casson Leighton --- ok there are a few things going on here. the CSV File always directs to the SPR FU. i've added a filter which allows the CSV entry to get through to the MMU FU. then stopped non-MMU SPR requests from getting to the SPR FU and only allowed them to get to the MMU FU. then also i had to fix the MMU FSM to get it to store in the SPR regfile. also, the unit test was wrong. you can't give a FU things that it is incapable of processing. the MMU FSM cannot cope with SPRs numbered 720 for example. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Mar 2 18:14:42 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 02 Mar 2021 18:14:42 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #3 from Luke Kenneth Casson Leighton --- design discussed here http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-March/002061.html RADIX Mem class to be added as an option that has a Mem class as a member instance and treats that as "Physical" memory. exact same API. class RADIXMem: self.mem = Mem() def ld(.....) def st(.....) -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 3 12:49:35 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 03 Mar 2021 12:49:35 +0000 Subject: [Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=583 --- Comment #45 from Luke Kenneth Casson Leighton --- hi Cesar i took a look at the pc_i.ok this morning, yes you are right, things will go awry with SVSTATE because we are currently not also setting SVSTATE from the debug interface. SVSTATE.srcstep (and dststep) are actual Sub-PC steppers so not resetting those is quite serious. for now what i suggest is to reset SVSTATE.srcstep and dststep to zero when pc_i.ok is raised high (i will take care of this) also as you suggested have pc_i.ok come on to the issue FSM and exit the loop. later we can add SVSTATE to the DMI (and JTAG), then the rule will have to be set, "please over DMI modify PC first then SVSTATE second". also then have to get test_core.py to use the DMI interface to set SVSTATE rather than put it into a SPR. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 3 12:51:34 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 03 Mar 2021 12:51:34 +0000 Subject: [Libre-soc-bugs] [Bug 609] New: set SVSTATE over DMI and JTAG interface Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=609 Bug ID: 609 Summary: set SVSTATE over DMI and JTAG interface Product: Libre-SOC's first SoC Version: unspecified Hardware: Other OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- SVSTATE contains the Sub-PC and needs to be given the same peer status as PC. that means adding to DMI and JTAG. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 3 13:07:11 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 03 Mar 2021 13:07:11 +0000 Subject: [Libre-soc-bugs] [Bug 609] set SVSTATE over DMI and JTAG interface In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=609 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |cestrauss at gmail.com Blocks| |583 See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=583 Referenced Bugs: https://bugs.libre-soc.org/show_bug.cgi?id=583 [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 3 13:07:11 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 03 Mar 2021 13:07:11 +0000 Subject: [Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=583 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Depends on| |609 See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=609 Referenced Bugs: https://bugs.libre-soc.org/show_bug.cgi?id=609 [Bug 609] set SVSTATE over DMI and JTAG interface -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 3 14:37:51 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 03 Mar 2021 14:37:51 +0000 Subject: [Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=583 --- Comment #46 from Luke Kenneth Casson Leighton --- i just added svstate_i which is the same as pc_i so that this can also be set whilst the processor is STOPPED. then, test_runner.py uses svstate_i.ok to set svstate and releases it at the same time as pc_i.ok when START is sent. in theeeeorryyyy that should solve the reset problem for starting a new program, because (just like pc_i) when the new svstate_i is passed in, it is no longer read from the StateRegs regfile. that was probably the problem. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Mar 4 17:27:57 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 04 Mar 2021 17:27:57 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #4 from Luke Kenneth Casson Leighton --- i went over the various implementations https://bugs.libre-soc.org/show_bug.cgi?id=604#c0 honestly i found it a bit of a nuisance :) the most obvious-looking (short once comments are removed) was gem5. one downside: we are NOT doing hypervisor... yet. so we need full compatibility with *microwatt* but microwatt is the least obvious because it is a FSM that communicates via handshakes with dcache / icache. bleh. also microwatt uses PIDR or something which is nonstandard, temporary until hypervisor is properly implemented. my feeling is, then, perhaps, create some ancillary functions such as a "permission checker" which uses microwatt rules. segment check for example: https://github.com/antonblanchard/microwatt/blob/6523acc74344b95e7cceb83611fb8cb2a030c1a3/mmu.vhdl#L338 and permission_check https://github.com/antonblanchard/microwatt/blob/6523acc74344b95e7cceb83611fb8cb2a030c1a3/mmu.vhdl#L362 i will just cut/paste stubs in niw, 1 sec -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Mar 4 17:48:10 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 04 Mar 2021 17:48:10 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #5 from Luke Kenneth Casson Leighton --- done, and also added pgtbl0/3. needs converting. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Mar 4 18:17:20 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 04 Mar 2021 18:17:20 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #6 from Luke Kenneth Casson Leighton --- whoops i just noticed that microwatt already allocates SPR 720 to PRTBL (a temporary non-official allocation), we were going to use that for SVSRR0 so i have moved SVSRR0 to 721. https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=0863c2918838890e88ef7d9f2ace66a8476fd3f2 tobias remember to do a git submodule update. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 5 09:54:44 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 05 Mar 2021 09:54:44 +0000 Subject: [Libre-soc-bugs] [Bug 595] Convert image(jpg,...) to svg In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=595 --- Comment #10 from vklr at vkten.in --- Drawed shadow.svg from jpg one. https://libre-soc.org/3d_gpu/shadow.svg Updated web page to include new one. https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ https://libre-soc.org/3d_gpu/architecture/6600scoreboard/discussion.mdwn Tell about payment. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 5 14:25:51 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 05 Mar 2021 14:25:51 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #7 from Luke Kenneth Casson Leighton --- tobias i am just putting in some leaf-node functions which i am taking from microwatt, like this: + def _decode_prte(self, data): + """PRTE0 Layout + ----------------------------------------------- + |/|RTS1|/| RPDB | RTS2 | RPDS | + ----------------------------------------------- + 0 1 2 3 4 55 56 58 59 63 + """ + zero = SelectableInt(0, 1) + rts = selectconcat(data[5:8], # [56-58] - RTS2 + data[61:63], # [1-2] - RTS1 + .... the idea is to put these functions together with meaningful names then work out how to join them up. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 5 16:31:23 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 05 Mar 2021 16:31:23 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #8 from Luke Kenneth Casson Leighton --- quick test done of _decode_prte and _segment_check: commit 60a226ae541d99e1c168984fa6ca8f4a4ed08e48 (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton Date: Fri Mar 5 16:16:41 2021 +0000 add segment_check function, plus quick test. also fix order because SelectableInt deals in BE tobias if you do the permissions check i will do a simple function which does prtable_addr pgtable_addr and pte from microwatt mmu.vhdl -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Mar 7 15:08:50 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 07 Mar 2021 15:08:50 +0000 Subject: [Libre-soc-bugs] [Bug 609] set SVSTATE over DMI and JTAG interface In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=609 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Status|CONFIRMED |IN_PROGRESS --- Comment #1 from Luke Kenneth Casson Leighton --- automatically gets added to JTAG which is pass-through on DMI commit 4d5482810c980ff927ccec62968a40a490ea86eb (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton Date: Sun Mar 7 15:05:24 2021 +0000 add SVSTATE read to DMI interface -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Mar 7 16:15:05 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 07 Mar 2021 16:15:05 +0000 Subject: [Libre-soc-bugs] [Bug 588] add SVP64 to PowerDecoder2 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=588 --- Comment #8 from Luke Kenneth Casson Leighton --- mode decoder here: https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64_rm.py;hb=HEAD mostly recognises the differences between standard RM Mode, LDST-immediate and LDST-indexed. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 00:17:29 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 00:17:29 +0000 Subject: [Libre-soc-bugs] [Bug 595] Convert image(jpg,...) to svg In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=595 --- Comment #11 from vklr at vkten.in --- Can I get payment for my work on two previous images. Do give me next image to work. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 00:33:05 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 00:33:05 +0000 Subject: [Libre-soc-bugs] [Bug 595] Convert image(jpg,...) to svg In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=595 --- Comment #12 from Luke Kenneth Casson Leighton --- yes, this is excellent quality work. we have to send an RFP to NLnet i will draft one for you. it takes around 2 weeks -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 03:54:35 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 03:54:35 +0000 Subject: [Libre-soc-bugs] [Bug 595] Convert image(jpg,...) to svg In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=595 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- The table of|vklr=100 |vklr=200 payments (in EUR)| | for this task;| | TOML format| | budget (EUR) for|100 |200 this task,| | excluding| | subtasks' budget| | total budget (EUR)|100 |200 for completion of| | task and all| | subtasks| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 03:54:56 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 03:54:56 +0000 Subject: [Libre-soc-bugs] [Bug 384] Documentation for the Libre-SOC POWER9 Core and internal architecture In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=384 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|4900 |4800 this task,| | excluding| | subtasks' budget| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 04:00:03 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 04:00:03 +0000 Subject: [Libre-soc-bugs] [Bug 611] New: ieee754fpu AddReduce broken Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=611 Bug ID: 611 Summary: ieee754fpu AddReduce broken Product: Libre-SOC's first SoC Version: unspecified Hardware: Other OS: Linux Status: CONFIRMED Severity: normal Priority: --- Component: ALU (including IEEE754 16/32/64-bit FPU) Assignee: lkcl at lkcl.net Reporter: programmerjake at gmail.com CC: libre-soc-bugs at lists.libre-soc.org, mail at awygle.com, programmerjake at gmail.com NLnet milestone: --- https://libre-soc.org/irclog/%23libre-soc.2021-03-07.log.html#t2021-03-07T22:06:30 > To Whom It May Concern - AddReduce is broken in part_mul_add/multiply.py, line 334, looks like some code got halfway migrated -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 04:04:19 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 04:04:19 +0000 Subject: [Libre-soc-bugs] [Bug 612] New: dev-env-setup script needed to build trellis and nextpnr-ecp5 Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 Bug ID: 612 Summary: dev-env-setup script needed to build trellis and nextpnr-ecp5 Product: Libre-SOC's first SoC Version: unspecified Hardware: Other OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Documentation Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- an automated script in dev-env-setup git repo is needed which gets nextpnr-ecp5 and all build dependencies (includes trellis) to work under debian 10 recommended to test it under a debootstrap of debian 10 to ensure all dependencies (apt get install) are correctly recorded. this involves python boost which is known to be an absolute nuisance. also updating HDL_workflow to include it, on a sub-page. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 04:04:40 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 04:04:40 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- Assignee|lkcl at lkcl.net |vklr at vkten.in -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 04:05:12 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 04:05:12 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- NLnet milestone|--- |NLNet.2019.10.Wishbone parent task for| |384 budget allocation| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 04:13:51 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 04:13:51 +0000 Subject: [Libre-soc-bugs] [Bug 611] ieee754fpu AddReduce broken In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=611 --- Comment #1 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part_mul_add/multiply.py;h=c9239fa6cccf970c34cdf2cf2c71339a4d25d8c0;hb=99586fc463c3a0932ae9ca3ac7c2f23a5b5e8c39#l332 missing n_inputs = followed by use at 332 and 334 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 08:16:02 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 08:16:02 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 --- Comment #1 from vklr at vkten.in --- Acknowledged. I will learn debootstrap and do. Any quick timeline within which to be done. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 11:25:15 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 11:25:15 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 --- Comment #2 from Luke Kenneth Casson Leighton --- it's not time-critical. also really should not take that long although that depends on capability of machine you have. start from this: https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-tools-yosys;hb=HEAD line 12-13 could be "mkdir fpga_tools" i have added you to dev-env-setup.git debootstrap is pretty damn easy. 2 lines. https://wiki.debian.org/Debootstrap main # mkdir /stable-chroot main # debootstrap stable /stable-chroot http://deb.debian.org/debian/ completing the install with the mount of proc and sysfs is important also you may find schroot helpful https://wiki.debian.org/Schroot you can see how to set up an automated schroot or at least see what commands to run https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=coriolis2-chroot;hb=HEAD ... actually i'm going to try creating a chroot-creating script, based on that. please do check it. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 16:28:41 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 16:28:41 +0000 Subject: [Libre-soc-bugs] [Bug 613] New: MESA3D: NIR/LLVM/x86 successful generation for simple shaders Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=613 Bug ID: 613 Summary: MESA3D: NIR/LLVM/x86 successful generation for simple shaders Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- see http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-March/002087.html -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 8 16:29:31 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 08 Mar 2021 16:29:31 +0000 Subject: [Libre-soc-bugs] [Bug 613] MESA3D: NIR/LLVM/x86 successful generation for simple shaders In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=613 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- parent task for| |251 budget allocation| | NLnet milestone|--- |NLNet.2019.Vulkan -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Mar 9 12:42:45 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 09 Mar 2021 12:42:45 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #9 from Luke Kenneth Casson Leighton --- tobias i moved the ISACaller RADIX class to a separate module, it's cleaner need to remove some imports now. i'm assuming you're keeping regularly up-to-date and have all commits pushed immediately at the time that they're confirmed working. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Mar 9 13:10:45 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 09 Mar 2021 13:10:45 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #10 from Luke Kenneth Casson Leighton --- added the perm check function. commit e440bd82392c798fe611abd89b3f25a331af2cca (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton Date: Tue Mar 9 13:09:35 2021 +0000 create first check_perms RADIX ISACaller function -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Mar 9 18:11:22 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 09 Mar 2021 18:11:22 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #11 from Luke Kenneth Casson Leighton --- commit d4809949497559f69c576838812b2282fe001d78 (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton Date: Tue Mar 9 18:09:53 2021 +0000 debug radix mmu ISACaller i managed to get the radix unit test pass, by adding __call__ as a duplicate of Mem.__call__ -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Mar 9 19:38:03 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 09 Mar 2021 19:38:03 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #12 from Luke Kenneth Casson Leighton --- i'm going to try this: @@ -189,7 +189,9 @@ class RADIX: def ld(self, address, width=8, swap=True, check_in_mem=False): print("RADIX: ld from addr 0x%x width %d" % (address, width)) - shift = SelectableInt(0, 32) + (shift, mbits, pgbase) = self._decode_prte(addr) + #shift = SelectableInt(0, 32) + you can see at line 235 and 315 in mmu.vhdl that pts is assigned to shift variable https://github.com/antonblanchard/microwatt/blob/6523acc74344b95e7cceb83611fb8cb2a030c1a3/mmu.vhdl#L235 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Mar 9 20:21:30 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 09 Mar 2021 20:21:30 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #13 from Luke Kenneth Casson Leighton --- from radixwalk.cc, walkTree needs to be: std::pair RadixWalk::walkTree(Addr vaddr , uint64_t curBase, BaseTLB::Mode mode, uint64_t curSize , uint64_t usefulBits) mode will be: * execute (instructions) * load or * store curSize and usefulBits are shift and mask curBase starts at the root page and works up from there. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Mar 9 22:30:25 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 09 Mar 2021 22:30:25 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 --- Comment #3 from vklr at vkten.in --- Setting up new Bootstrap and chroot into it export MY_CHROOT=/stable-chroot mkdir $MY_CHROOT debootstrap stable $MY_CHROOT http://deb.debian.org/debian/ mount -t proc proc $MY_CHROOT/proc mount -t sysfs sysfs $MY_CHROOT/sys mount -t devpts devpts $MY_CHROOT/dev/pts/ chroot $MY_CHROOT /bin/bash Steps to compile Project Trellis Necessary software to install apt-get install git apt-get install python3 python3-dev clang cmake libboost-dev libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev libboost-iostreams-dev openocd git clone --recursive https://github.com/YosysHQ/prjtrellis Build Project Trellis cd prjtrellis cd libtrellis cmake -DCMAKE_INSTALL_PREFIX=/usr/local/libtrellis . make make install Next I will find out procedure for nextpnr(-ecp5) -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Mar 9 23:47:41 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 09 Mar 2021 23:47:41 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 --- Comment #4 from vklr at vkten.in --- Steps to compile Project Nextpnr with ECP5 Necessary software to install apt-get install libeigen3-dev git clone --recursive https://github.com/YosysHQ/nextpnr Build Project nextpnr-ecp5 cd nextpnr cmake -DCMAKE_INSTALL_PREFIX=/usr/local/nextpnr-ecp5 -DARCH=ecp5 -DTRELLIS_INSTALL_PREFIX=/usr/local/libtrellis . make make install Please adjust the install paths for nextpnr and previous prjtrellis. Can you suggest a suitable filename for subpage in HDL_workflow. To be more clear do I have to put schroot steps in it. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 10 00:53:15 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 10 Mar 2021 00:53:15 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 --- Comment #5 from Luke Kenneth Casson Leighton --- (In reply to vklr at vkten.in from comment #4) > Steps to compile Project Nextpnr with ECP5 > > Necessary software to install excellent. > > Can you suggest a suitable filename for subpage in HDL_workflow. hmmm... i would say ECP5 but that is taken. HDL_workflow/nextpnr sound good? > To be more clear do I have to put schroot steps in it. no, i simply created the schroot script to make it easier and quicker for you to double-check -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 10 09:32:16 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 10 Mar 2021 09:32:16 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 --- Comment #6 from vklr at vkten.in --- Added nextpnr page: https://libre-soc.org/HDL_workflow/nextpnr/ Added nextpnr section to page: https://libre-soc.org/HDL_workflow/ Review and give suggestions. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 10 18:22:45 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 10 Mar 2021 18:22:45 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 --- Comment #7 from Luke Kenneth Casson Leighton --- (In reply to vklr at vkten.in from comment #6) > Added nextpnr page: https://libre-soc.org/HDL_workflow/nextpnr/ > > Added nextpnr section to page: https://libre-soc.org/HDL_workflow/ > > Review and give suggestions. great, i made some minor formatting changes, to use markdown "indentation" (four spaces) https://libre-soc.org/HDL_workflow/nextpnr/?updated great, next step: * git clone gitolite3 at git.libre-soc.org:dev-env-setup.git * run (create) a completely new chroot * make a "nextpnr-ecp5-install" script * add all those commands (from the new nextpnr page) to that script * test it and make sure that you have not missed any dependencies * git add, commit and push the (tested) nextpnr-ecp5-install script btw for goodness sake DO NOT blow away the "old" chroot WITHOUT FIRST UNMOUNTING THE mount-points. if you do "rm -fr /opt/chroot/whatever" it will try to blow away /tmp, /proc and other locations so mounted. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Mar 11 11:36:43 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 11 Mar 2021 11:36:43 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #14 from Luke Kenneth Casson Leighton --- continued from here: http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-March/002121.html turns out i did think about this: https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/isa/mem.py;h=723fca0980d2d35d2dd12f9fc1f0d8bd325f7569;hb=5963eef6679f6833b6b8f854868d90480e3753b2#l36 that's a dictionary, not a list. so it should be good to use the example from here: https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/mmu/test/test_issuer_mmu_rom.py;h=2552b14b03bb5ac08c6a14f86bac3694f1220500;hb=5963eef6679f6833b6b8f854868d90480e3753b2#l15 if you take a copy of that dictionary *make sure to document that fact* in both files. better to move it to a separate file (on its own) and import it from both unit tests. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Mar 11 18:20:48 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 11 Mar 2021 18:20:48 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #15 from Luke Kenneth Casson Leighton --- commit 8e4b1c04b2e7fd655f9a35e796028a41a756cf1b (HEAD -> master) Author: Luke Kenneth Casson Leighton Date: Thu Mar 11 18:19:43 2021 +0000 whoops PIDR is defined as 32-bits in SPRs.csv (and spec) tobias i'd assumed PIDR was 64 bit, it's actually 32. effpid = pid #self.pid # TODO, check on this -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Mar 11 18:58:35 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 11 Mar 2021 18:58:35 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #16 from Tobias Platen --- > if you take a copy of that dictionary *make sure to document that fact* in both > files. better to move it to a separate file (on its own) and import it from > both unit tests. I'm going to do that. But for any reason I do not receive emails from the mailing list. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Mar 11 19:16:16 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 11 Mar 2021 19:16:16 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #17 from Luke Kenneth Casson Leighton --- (In reply to Tobias Platen from comment #16) > But for any reason I do not receive emails from the mailing list. your server's currently rejecting messages (server configuration problem, 451) -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 12 06:10:04 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 12 Mar 2021 06:10:04 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 --- Comment #8 from vklr at vkten.in --- Added nextpnr-ecp5-install script to dev-env-setup.git url: https://git.libre-soc.org/?p=dev-env-setup.git;a=blob_plain;f=nextpnr-ecp5- install;hb=HEAD Adjust the installation path of libtrellis and nextpnr if need. e.g. to install them to /usr/local instead. Also the proc, sysfs and devpts are mounted and unmounted within the script. If not needed comment them out. Review and give suggestions. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 12 10:31:26 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 12 Mar 2021 10:31:26 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 --- Comment #9 from Luke Kenneth Casson Leighton --- ok looks good, i removed the mount/unmount because this will end up being run outside of chroot. also keeping it to under 80 chars. can you copy the style of hdl-tools-yosys, use "make -j$(nproc) and do the same preamble as in hdl-dev-repos. hmmm all these scripts need to be cd /home/$SUDO_USER/src -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 12 10:38:28 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 12 Mar 2021 10:38:28 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 --- Comment #10 from Luke Kenneth Casson Leighton --- all of the build scripts are a bit of a mess i've cleaned them up to build in a consistent location, /home/$SUDO_USER/src please do git pull -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 12 11:58:03 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 12 Mar 2021 11:58:03 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 --- Comment #11 from vklr at vkten.in --- Added make parallelization. chown and chgrp the downloaded repo's. Review. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 12 16:52:02 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 12 Mar 2021 16:52:02 +0000 Subject: [Libre-soc-bugs] [Bug 384] Documentation for the Libre-SOC POWER9 Core and internal architecture In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=384 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- budget (EUR) for|4800 |4650 this task,| | excluding| | subtasks' budget| | -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 12 16:53:57 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 12 Mar 2021 16:53:57 +0000 Subject: [Libre-soc-bugs] [Bug 612] dev-env-setup script needed to build trellis and nextpnr-ecp5 In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=612 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- total budget (EUR)|0 |150 for completion of| | task and all| | subtasks| | Status|CONFIRMED |RESOLVED Resolution|--- |FIXED The table of| |"vklr"=150 payments (in EUR)| | for this task;| | TOML format| | budget (EUR) for|0 |150 this task,| | excluding| | subtasks' budget| | --- Comment #12 from Luke Kenneth Casson Leighton --- that looks great. closing as resolved, can you link this on your page... ah! you already have! :) https://libre-soc.org/veera/ -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Mar 13 18:12:02 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sat, 13 Mar 2021 18:12:02 +0000 Subject: [Libre-soc-bugs] [Bug 587] create setvl pseudocode, v3.0B fields, SVL-Form, and csv file In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=587 --- Comment #4 from Luke Kenneth Casson Leighton --- https://libre-soc.org/openpower/isa/simplev/ pseudocode added https://libre-soc.org/openpower/isatables/minor_22.csv and setvl CSV https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=c94a0187816c484030cf7d0b9a47b8951dcb8d41 and unit tests -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Mar 13 23:55:57 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sat, 13 Mar 2021 23:55:57 +0000 Subject: [Libre-soc-bugs] [Bug 594] create nmigen RFC for Dynamic Partitioned signals support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=594 --- Comment #2 from Luke Kenneth Casson Leighton --- discussion about whether PartitionedBool would be necessary https://libre-soc.org/irclog/%23libre-soc.2021-03-13.log.html#t2021-03-13T23:49:13 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Mar 14 12:58:57 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 14 Mar 2021 12:58:57 +0000 Subject: [Libre-soc-bugs] [Bug 613] MESA3D: NIR/LLVM/x86 successful generation for simple shaders In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=613 --- Comment #1 from Luke Kenneth Casson Leighton --- also: http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-March/002154.html -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 15 17:38:17 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 15 Mar 2021 17:38:17 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #18 from Tobias Platen --- email now working correctly -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Mar 16 20:25:32 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 16 Mar 2021 20:25:32 +0000 Subject: [Libre-soc-bugs] [Bug 602] low performance bare minimum functionality SIMD emulator required In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=602 --- Comment #8 from Richard Wilbur --- You mentioned ISA v3.0B: Did you mean "PowerISA_public.v3.0B.pdf"? Or should we go for what looks like newer documentation in "PowerISA_public.v3.0C.pdf" or "PowerISA_10_public_v3.1.pdf"? I guess I'm not familiar with the provenance of these documents. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 00:01:40 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 00:01:40 +0000 Subject: [Libre-soc-bugs] [Bug 616] New: duplicate entries in comment field Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=616 Bug ID: 616 Summary: duplicate entries in comment field Product: Libre-SOC's first SoC Version: unspecified Hardware: Other OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: programmerjake at gmail.com CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/isatables/minor_30.csv;h=b2c8e9138f87ec898459e4bab4a424b35bfce04c;hb=HEAD -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 00:28:24 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 00:28:24 +0000 Subject: [Libre-soc-bugs] [Bug 616] duplicate entries in comment field In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=616 --- Comment #1 from Luke Kenneth Casson Leighton --- ok these ones are fine because the lines are identical, ah but wait... when creating the RM*.csv files some lines will be missed. nuts. sv_analysis.py now needs to have the primary key changed to be a tuple of (comment,opfield) so as to be unique. really, though, the CSV files should be using wildcard "don't care" patterns 0b0111- rather than 0b01110 0b01111 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 10:21:50 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 10:21:50 +0000 Subject: [Libre-soc-bugs] [Bug 602] low performance bare minimum functionality SIMD emulator required In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=602 --- Comment #9 from Luke Kenneth Casson Leighton --- (In reply to Richard Wilbur from comment #8) > You mentioned ISA v3.0B: > > Did you mean "PowerISA_public.v3.0B.pdf"? > Or should we go for what looks like newer documentation in > "PowerISA_public.v3.0C.pdf" or "PowerISA_10_public_v3.1.pdf"? I guess I'm > not familiar with the provenance of these documents. they're both the same except a preamble at the front for Compliance Subsets. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 12:35:47 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 12:35:47 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #19 from Luke Kenneth Casson Leighton --- tobias i just added an extra argument to Mem and RADIXMMU classes, "instr_fetch". this is crucial to detecting "Execute" in the permission check function at the minimum. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 13:20:07 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 13:20:07 +0000 Subject: [Libre-soc-bugs] [Bug 617] New: add SVP64 predication to TestIssuer Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 Bug ID: 617 Summary: add SVP64 predication to TestIssuer Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- predication needs to be added to TestIssuer, both single and twin -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 13:21:06 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 13:21:06 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=583 Assignee|lkcl at lkcl.net |cestrauss at gmail.com Depends on| |588 URL| |https://libre-soc.org/openp | |ower/sv/implementation/ Referenced Bugs: https://bugs.libre-soc.org/show_bug.cgi?id=588 [Bug 588] add SVP64 to PowerDecoder2 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 13:21:06 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 13:21:06 +0000 Subject: [Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=583 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=617 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 13:29:41 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 13:29:41 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #1 from Luke Kenneth Casson Leighton --- Cesar i've added a couple of extra ports so as to be able to read the predicates. INT will be easier, it can be done one-shot. CR is different, a little more complex. diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index aec56e44..2512d3ae 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -77,6 +77,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray): self.r_ports = {'ra': self.read_port("src1"), 'rb': self.read_port("src2"), 'rc': self.read_port("src3"), + 'pred': self.read_port("pred"), # for predicate mask 'dmi': self.read_port("dmi")} # needed for Debug (DMI) @@ -129,6 +130,7 @@ class CRRegs(VirtualRegPort): 'cr_b': self.write_port("dest2")} # 4-bit, unary-indexed self.r_ports = {'full_cr': self.full_rd, # 32-bit (masked, 8-en lines) 'full_cr_dbg': self.full_rd2, # for DMI + 'cr_pred': self.read_port("cr_pred"), # for predicate 'cr_a': self.read_port("src1"), 'cr_b': self.read_port("src2"), 'cr_c': self.read_port("src3")} -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 15:21:57 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 15:21:57 +0000 Subject: [Libre-soc-bugs] [Bug 618] New: add SVP64 predication to ISACaller Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=618 Bug ID: 618 Summary: add SVP64 predication to ISACaller Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- both single and twin predication needs adding to ISACaller simulator, for CR and INT sources. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 15:22:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 15:22:39 +0000 Subject: [Libre-soc-bugs] [Bug 618] add SVP64 predication to ISACaller In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=618 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=583, | |https://bugs.libre-soc.org/ | |show_bug.cgi?id=617 Blocks| |241 Referenced Bugs: https://bugs.libre-soc.org/show_bug.cgi?id=241 [Bug 241] OpenPOWER SImulation is needed of standards -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 15:22:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 15:22:39 +0000 Subject: [Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=583 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=618 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 15:22:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 15:22:39 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=618 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 15:23:08 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 15:23:08 +0000 Subject: [Libre-soc-bugs] [Bug 618] add SVP64 predication to ISACaller In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=618 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- URL| |https://libre-soc.org/openp | |ower/sv/implementation/ --- Comment #1 from Luke Kenneth Casson Leighton --- commit 379cc6df93eec26dae0fc523b18a1996f1e90d97 (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton Date: Wed Mar 17 15:20:02 2021 +0000 add SVP64 INT-style predication to ISACaller -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 20:42:53 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 20:42:53 +0000 Subject: [Libre-soc-bugs] [Bug 618] add SVP64 predication to ISACaller In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=618 --- Comment #2 from Luke Kenneth Casson Leighton --- commit 4a62e46f76219b3c02fee379047d8a18df2f22fc (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton Date: Wed Mar 17 20:40:49 2021 +0000 add CR-based predication to ISACaller -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 17 22:16:54 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 17 Mar 2021 22:16:54 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #2 from Luke Kenneth Casson Leighton --- Cesar when it comes to it, here's how to skip over src and dest elements that have predication bits zero: while (((1< https://bugs.libre-soc.org/show_bug.cgi?id=619 Bug ID: 619 Summary: CSV file mess associated with lack of "out2" column Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Source Code Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- summarised as "argh". http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-March/002195.html this bugreport serves to keep track of places where the "fake" creation of out2 is hard-coded. if not tracked it will be extremely difficult to retain consistency. edit this comment to add locations: https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;h=d6e3b039a978b3e542483533088852aec21c55c3;hb=1267f463aa6da5f0062961657fda303e8efc70f3#l365 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Mar 18 12:40:10 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 18 Mar 2021 12:40:10 +0000 Subject: [Libre-soc-bugs] [Bug 586] microwatt SVP64-equivalent of decode1.vhdl to be autogenerated In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=586 --- Comment #3 from Luke Kenneth Casson Leighton --- commit 00c03aad232bdfb4cf20d6afec12247b91105f97 (HEAD -> master, origin/master, origin/HEAD) Author: Luke Kenneth Casson Leighton Date: Thu Mar 18 12:36:46 2021 +0000 update microwatt sv_decode.vhdl prototype with new sv_out2 column https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=00c03aad232bdfb4cf20d6afec12247b91105f97 two changes: 1) the RS has been moved 2) a new "out2" column has been added including which EXTRA2/3 is used to extend it -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Mar 18 14:26:46 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 18 Mar 2021 14:26:46 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #3 from Luke Kenneth Casson Leighton --- so, just so you know, the final pseudo-code will be something like this: if not src_zeroing: while (((1< References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #20 from Luke Kenneth Casson Leighton --- just put in read of MSR.PR bit for "priv". i've no idea which way round it should be set :) i have a thought that it may be a good idea to create and raise actual exceptions (in python) then catch them back in ISACaller and call ISACaller.trap() with the right arguments (right exception address/type). -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Mar 18 19:16:08 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 18 Mar 2021 19:16:08 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #4 from Luke Kenneth Casson Leighton --- added a stub here: def fetch_predicate_fsm(self, m, core, TODO): """fetch_predicate_fsm - obtains (constructs in the case of CR) src/dest predicate masks -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Thu Mar 18 21:21:43 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Thu, 18 Mar 2021 21:21:43 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #5 from Luke Kenneth Casson Leighton --- here's how CR predication is read in ISACaller, it is done as a for-loop from 0 to VL-1, *in advance* of execution. https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/isa/caller.py;hb=74e1cb79e40d1a7c66f7ad0b942cbe654859eeda#l250 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 19 20:35:05 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 19 Mar 2021 20:35:05 +0000 Subject: [Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=583 --- Comment #47 from Cesar Strauss --- (In reply to Cesar Strauss from comment #41) > I have split the new issue FSM out from the issue/execute FSM, and marked > the places where the looping will be checked/done, and where PC/SRCSTEP will > be updated. This is old news by now, but, for the record, the Issue FSM now implements the SRCSTEP VL loop, as well as the VL==0 vector skip loop. Probably, the VL==0 loop could have been done in Fetch instead. Luke, do you want me to do this, before moving to predication, or leave it for later? -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 19 21:41:31 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 19 Mar 2021 21:41:31 +0000 Subject: [Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=583 --- Comment #48 from Luke Kenneth Casson Leighton --- (In reply to Cesar Strauss from comment #47) > Probably, the VL==0 loop could have been done in Fetch instead. Luke, do you > want me to do this, before moving to predication, or leave it for later? let's start predication, see how that goes, i will update comment 0 to make sure it's TODO or at least raised a new bugreport -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Mar 20 11:56:55 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sat, 20 Mar 2021 11:56:55 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #6 from Luke Kenneth Casson Leighton --- (In reply to Luke Kenneth Casson Leighton from comment #3) > so the first phase is to add src-step and dst-step "skipping", based > on which bits of the predicate mask(s) are zero this bit is fairly easy and involves TestIssuer FSM only. > the second phase adds in src_zeroing / dest_zeroing which does NOT > skip the computation but instead feeds **ZEROs** into either the > input or the output this one is very intrusive into the Core class because it stops read and write of registers. in ISACaller it is relatively straightforward to do this, but hooking into Core connections to the regfiles requires masking and telling the CompUnits they do not need to read/write regfiles. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Mar 20 12:06:04 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sat, 20 Mar 2021 12:06:04 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #7 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/isa/caller.py;h=b52f88c5db016b57ca2aaf070c31e48d58d135e2;hb=405f5eee9d01ab896d4d85df7df4921d3a4a422b#l963 zeroing detected here for this src/dst step, by ANDing the mask bit. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Mar 20 15:20:00 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sat, 20 Mar 2021 15:20:00 +0000 Subject: [Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=517 --- Comment #72 from Luke Kenneth Casson Leighton --- https://github.com/arduino/OpenOCD/blob/master/tcl/interface/stlink-v2.cfg that's how to tell openocd to use an stlinkv2. trying to use this file: https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=openocd.cfg;hb=HEAD clearly isn't going to work, because, obviously, right at the start, it says, "connect to jtagremote" not "connect to stlinkv2". -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sat Mar 20 16:18:37 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sat, 20 Mar 2021 16:18:37 +0000 Subject: [Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=517 --- Comment #73 from Luke Kenneth Casson Leighton --- https://gitlab.com/Chips4Makers/Retro-uC/-/tree/master/boards/XLR8/demo -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Mar 21 13:12:58 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 21 Mar 2021 13:12:58 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #8 from Luke Kenneth Casson Leighton --- cesar, my thoughts are that running the pipelines with zero inputs is not useful, and that instead this is more useful and less... puzzling: if (src_zeroing and ((1< References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #9 from Luke Kenneth Casson Leighton --- commit 49b01d0c4382c4035fa7274d5051a6e36a85a2a0 (HEAD -> master) Author: Luke Kenneth Casson Leighton Date: Sun Mar 21 13:25:26 2021 +0000 code comments in TestIssuer -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Mar 21 21:54:27 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 21 Mar 2021 21:54:27 +0000 Subject: [Libre-soc-bugs] [Bug 587] create setvl pseudocode, v3.0B fields, SVL-Form, and csv file In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=587 --- Comment #5 from Luke Kenneth Casson Leighton --- i worked out that there is (just about) space to fit setvl into the bitmanip EXT22 sandbox encoding. XO is set to 0b11110 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 22 04:58:54 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 22 Mar 2021 04:58:54 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #10 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=b63f2dcfaac1a7527a0007950913dffb30dc99e2 whoops i forgot to say that when get_intpred returns zero in the reg number it means "use always" i.e. 0b1111111111... -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 22 22:20:54 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 22 Mar 2021 22:20:54 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #11 from Luke Kenneth Casson Leighton --- cesar, it looks like there needs to be an extra state which goes here: https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer.py;hb=HEAD#l573 or, perhaps, inside the predicate fsm, advances srcstep/dststep there, before indicating that execute is to proceed? i can see otherwise that quite a lot of wait states would be introduced. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Tue Mar 23 03:53:18 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Tue, 23 Mar 2021 03:53:18 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #12 from Luke Kenneth Casson Leighton --- (In reply to Luke Kenneth Casson Leighton from comment #11) > or, perhaps, inside the predicate fsm, advances srcstep/dststep there, > before indicating that execute is to proceed? nope, because that is once per instruction, and the skipping needs to be per VL loop -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 24 05:12:32 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 24 Mar 2021 05:12:32 +0000 Subject: [Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=617 --- Comment #13 from Luke Kenneth Casson Leighton --- for skipping it is probably simpler and shorter to use this: * already_done = (1< References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #21 from Luke Kenneth Casson Leighton --- https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/isa/radixmmu.py;h=10b95ff084e51e04229bac6d1c7d21c24394427b;hb=23d5a669f0e7193359a262e3e34a44b10e007e23#l489 that should be "nonzero != 0" -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Wed Mar 24 10:20:10 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Wed, 24 Mar 2021 10:20:10 +0000 Subject: [Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=604 --- Comment #22 from Luke Kenneth Casson Leighton --- (In reply to Luke Kenneth Casson Leighton from comment #21) > that should be "nonzero != 0" done. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 26 11:49:09 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 26 Mar 2021 11:49:09 +0000 Subject: [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=577 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://bugs.libre-soc.org/ | |show_bug.cgi?id=615 -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Fri Mar 26 12:12:46 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Fri, 26 Mar 2021 12:12:46 +0000 Subject: [Libre-soc-bugs] [Bug 577] gcc compiler, binutils and assembly macros for OpenPOWER-SV In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=577 --- Comment #1 from Luke Kenneth Casson Leighton --- in issue #615 i am keeping notes from various conversations with ppc binutils and gcc maintainers, as well as OPF. summary of OPF advice: an architectural fork inside gcc will not be well received due to the implication of ecosystem fragmentation. one idea came up from David to use the same trick intended for v3.1: there they intend mark entries in rs6000.md as "v3.1prefixableto64bit", and David said he would have no problem with us doing the same thing: set attribute "svp64vectoriseable". for us this would indicate that when it came to assembly output there would be a special 32bit EXT01 assembly instruction outputted at the front of any instruction marked with the attribute. Segher then suggested *redefining* the underlying data structure that is used by the macro system for representing registers. this combination effectively empowers all svp64-marked macro patterns to have a massive addition set of matching capabilities. on registers alone this would be: * RT=s RA=s RB=s * RT=v RA=s RB=s * .... * RT=v RA=v RB=v when element-width overrides are introduced these permutations multiply by 4 for source elwidth override *and another* four for dest elwidth override. when additional capabilities such as a saturation are also added, the thought of creating a macro file even one that is autogenerated with all these permutations *per macro* listed explicitly is, at best, described as insane and, frankly, stupid. a little intelligent thought shows that the pattern-matching can be done implicitly (using existing rs6000.md patterns) when marked with an appropriate attribute. this will allow us to do very basic (and i mean very basic) matching between vector patterns and svp64-attribute-marked rs6000.md macros. anything not part of a conditional if/else computation for example: straight unconditional for-loops. where it gets more complicated is anything that's computed which is to be used for a branch decision. this requires predication (like is used in arm32bit) which is not a "normal" part of ppc except in very special unique circumstances. avoiding that situation for now and simply doing unconditional for-loop expansion would still be a huge leap forward. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Sun Mar 28 12:53:39 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Sun, 28 Mar 2021 11:53:39 +0000 Subject: [Libre-soc-bugs] [Bug 276] SR NAND Latch needed in nmigen In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=276 --- Comment #19 from Luke Kenneth Casson Leighton --- very useful tutorial / demo on cxxrtl simulation https://tomverbeure.github.io/2020/08/08/CXXRTL-the-New-Yosys-Simulation-Backend.html -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 29 12:29:11 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 29 Mar 2021 11:29:11 +0000 Subject: [Libre-soc-bugs] [Bug 578] python-based svp64 "generator" class In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=578 Luke Kenneth Casson Leighton changed: What |Removed |Added ---------------------------------------------------------------------------- URL| |https://libre-soc.org/openp | |ower/sv/implementation/ -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 29 13:26:31 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 29 Mar 2021 12:26:31 +0000 Subject: [Libre-soc-bugs] [Bug 203] potential improvements to coriolis2 for LibreSOC Layout In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=203 --- Comment #3 from Luke Kenneth Casson Leighton --- *huge* amount of work gone in here, including antenna, buffers, IO pad ring redesign. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 29 13:28:03 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 29 Mar 2021 12:28:03 +0000 Subject: [Libre-soc-bugs] [Bug 204] Transition from symbolic to real Cell Library for 180nm layout In-Reply-To: References: Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=204 --- Comment #5 from Luke Kenneth Casson Leighton --- symbolic layout is now possible with FreePDK45. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 29 13:32:46 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 29 Mar 2021 12:32:46 +0000 Subject: [Libre-soc-bugs] [Bug 620] New: post-layout simulation needed using cocotb Message-ID: https://bugs.libre-soc.org/show_bug.cgi?id=620 Bug ID: 620 Summary: post-layout simulation needed using cocotb Product: Libre-SOC's first SoC Version: unspecified Hardware: PC OS: Linux Status: CONFIRMED Severity: enhancement Priority: --- Component: Hardware Layout Assignee: lkcl at lkcl.net Reporter: lkcl at lkcl.net CC: libre-soc-bugs at lists.libre-soc.org NLnet milestone: --- taking the VST (VHDL) files from coriolis2 post-layout modifications (including insertion of buffers) needs to be verified. this to be done using cocotb to connect up to JTAG (c4m-jtag) and perform tests. -- You are receiving this mail because: You are on the CC list for the bug. From bugzilla-daemon at libre-soc.org Mon Mar 29 13:33:16 2021 From: bugzilla-daemon at libre-soc.org (bugzilla-daemon at libre-soc.org) Date: Mon, 29 Mar 2021 12:33:16 +0000 Subject: [Libre-soc-bugs] [Bug 620] post-layout simulation needed using cocotb In-Reply-To: