[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #17 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #16)
> Staf: we still need that cell library (aka liberty file) with just the one
> item in it: SPBlock_512W64B8W
> 

I propose to use Verilog files to define blackboxes for yosys. This would as
follows for the SRAM bock:

    (* blackbox = 1 *)
    module SPBlock_512W64B8W(input [8:0] a, input [63:0] d, output [63:0] q,
input [7:0] we, input clk);
    endmodule // SPBlock_512W64B8W

This has been tested to work by Jean-Paul and support it has been added to the
Coriolis flow.

I also noticed that I did not connect pin to the SRAM block in previous code.
The nmogen code should be:

    a = Signal(9)
    q = Signal(64)
    d = Signal(64)
    we = Signal(8)
    sram = Instance(
"SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we, i_clk=ClockSignal())
    m.submodules += sram

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