[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Cesar would you like to plan / draw out a FSM which splits TestIssuer into
2 FSMs?

the first FSM should be IDLE and INSN_READ, to be joined by INSN_WAIT

the second FSM should be what is currently INSN_START and INSN_ACTIVE.
these will need to be joined in this 2nd FSM by an IDLE state which
the first FSM triggers.

with ready/valid signalling it should be possible to get FSM1 to trigger
FSM2 to move to the new state, and likewise FSM2 to trigger FSM1 to move
back to IDLE.

the first phase is *not* to add SV support straight away.  the idea
is to change the *v3.0B* TestIssuer to 2 FSMs, with no change in behaviour.
v3.0B instruction read/issue *only*.

then once that is done it becomes much easier to get the 1st FSM to read
64-bit instructions, than it is right now.

one other nice thing is that the two FSMs will allow us to do pipelined
versions later, much more easily.

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