[Libre-soc-bugs] [Bug 581] power-gem5 needs upstream merging

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=581

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
>> cross-verifying register contents between a gem5 and qemu (user-mode) runs
>> of small assembly programs covering the corner cases of each instruction.
>> In your case, this will be something like:
>>
>> $ ./build/POWER/gem5.debug configs/example/se.py --wait-gdb -c ~/test
>
> that's exactly it.  thank you that will save a huge amount of time.
> have you made the unit test programs available?  also, you may be

Glad you found it to be useful. I have some old test programs here at
https://bitbucket.org/sandip4n/gem5-powerpc64le-tests

These were written a while back when I was still learning powerpc
assembly and upon a quick inspection, it seems that the stack frame
setup is semantically incorrect. As in, those stw/stwu instructions
should have been std/stdu. The test cases might still be salvageable.

> interested to know that anton blanchard wrote a
> random-program-generator, they're checked in here
> https://github.com/antonblanchard/microwatt/tree/master/tests
>

Nice! I'll check it out. A colleague had also pointed me to something
similar for qemu called risu which is available at
https://git.linaro.org/people/peter.maydell/risu.git

This tool can also generate random instruction sequences and compare
the results with a real system.

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