[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_svp64.py;hb=HEAD

hmm hmm as-is this is not very useful.

what is needed is to be able to get bits from EXTRA2/3 fields and say "this one
extends RA".

right now it is inverted, key us value, value is key.

a bit more post-processing is needed, examining the v3.0B fields IN1, IN2, etc,
to create:

SVP64_IN1, SVP64_IN2

and for those fields to contain the index 0, 1, 2, 3 pointing to which bits of
RM to read.

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