[Libre-soc-bugs] [Bug 580] PowerDecoder needs to redirect MMU SPRs to the MMU

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=580

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
excellent, saw the commits.  am just doing some whitespace cleanup
(please keep an eye on that).

also do use the power_enums SPR class/instance to do "SPR.DSISR" (something
like that) rather than hard-coded numbers that will mean nothing to
people unfamiliar with the 1,300 page technical reference manual

lkcl at fizzy:~/src/libresoc/soc/src/soc$ python3 decoder/power_enums.py 
SPR.TAR
SPR.XER 1 SPR.XER XER
SPR.DSCR 3 SPR.DSCR DSCR
SPR.LR 8 SPR.LR LR
SPR.CTR 9 SPR.CTR CTR
SPR.AMR 13 SPR.AMR AMR
SPR.DSCR_priv 17 SPR.DSCR_priv DSCR_priv
SPR.DSISR 18 SPR.DSISR DSISR
SPR.DAR 19 SPR.DAR DAR

commit 1f7f510c9b03d3646a52153874b37f33062b9ae5 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed Jan 27 12:35:30 2021 +0000

    whitespace and shortening of SPR MMU redirection in Power Decoder

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