[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #2)
> (In reply to Cesar Strauss from comment #0)
> >     a) if a SVP64 prefix was decoded, read and decode the next word, before
> > really issuing the instruction

yes.  basically, with a FSM though you have to be careful.  the actual PC is at
the EXT001 (the prefix) not the suffix part!

but you still have to *read* both the prefix and suffix.

one possible solution is to have two FSMs, one for reading instructions, one
for processing them.  they communicate by signals to say "start" and "done"
just like ready/valid.

that way, passing 64 bit or 32 bit it is all the same.

> Also, if VL is zero, do not issue any vector instruction, just keep fetching
> the next instruction.

yes, because the for loop is from 0 to 0.

of course if it is a v3.0B 32bit instruction VL does not apply so will always
be executed.

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