[Libre-soc-bugs] [Bug 583] New: Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

            Bug ID: 583
           Summary: Implement simple VL for-loop in nMigen for TestIssuer
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
               URL: https://libre-soc.org/openpower/sv/implementation/
                OS: Linux
            Status: IN_PROGRESS
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: cestrauss at gmail.com
          Reporter: cestrauss at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

The goal is to implement the following pseudo-code

   for i = 0 to VL-1:
       GPR(RT+i) = GPR(RA+i) + GPR(RB+i)

The tasks are:

1) add SVSTATE as an SPR

2) augment PowerDecoder to decode the SVP64 prefix

3) augment the TestIssuer FSM to:

    a) if a SVP64 prefix was decoded, read and decode the next word, before
really issuing the instruction

    b) issue the instruction and wait for completion.

    c) If any source or destination was a vector, keep issuing the instruction
and increment SVSTATE.srcstep. Break when it reaches VL-1

    d) set SVSTATE.srcstep to zero again


4) modify the read/write point in the regfile to add SVSTATE.srcstep to
the reg number

5) add SETVL instruction

6) figure out how to deal with exceptions in the middle of a vector
instruction:

   a) save the SVSTATE before entering an exception.

   b) when exiting, restore SVSTATE, while setting the PC to the current
instruction, so it's decoded and issued again.

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