[Libre-soc-bugs] [Bug 578] python-based svp64 "generator" class

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=578

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
to get the register order a few hoops have to be jumped through.  the
information needed is:

* to identify which arguments are registers and which are immediates.

example:

   cmp BF,L,RA,RB

* BF is a CR
* RA and RB are registers

here is a file which contains that information:

   
https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/isa/comparefixed.mdwn;hb=HEAD

here is the program that extracts that information:

   
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/pseudo/pagereader.py;hb=HEAD

now, these are just the names and the order.  but, the svp64 prefix
needs to know the format (order) for the R_EXTRA2/3 section of the
Remapped Encoding
    (see https://libre-soc.org/openpower/sv/svp64/)

*that* information is in the CSV files, generated by sv_analysis.py

   
https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD

running that program will generate some svp64 "RM-XX-YYZZ" files, with
the following format and columns:

    insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out
    cmp,1P,EXTRA3,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF

note that the format here says "EXTRA3", this tells us "3 bits per
register" in the Extra Remapped Encoding bits

and the numbering 0,1,2,3 tells us that:

* BF extension is to go into the first 3 bits
* RA extension is to into the second 3 bits
* RB extension is to go inth the third 3 bits

how do we get the information about which was BF, which was RA, which was RB?
we get that information by using pagereader.py to get the parameters

    cmp BF,L,RA,RB

L may be ignored (or, more: unmodified)

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