[Libre-soc-bugs] [Bug 558] gcc SV intrinsics concept

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=558

--- Comment #64 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
briefly (more tomorrow):

* https://libre-soc.org/openpower/isa/condition/

  cr ops would be fine to Vectorise
  vertically

* https://libre-soc.org/openpower/isa/sprset/

  mtcrf which is a multi-bit (8 bit mask)
  field, FXM, is *NOT* fine to Vectorise

  or if it is, it would have to be done
  as a FSM by reading "columns" of CRs,
  one for each "bit" in FXM.  if 5 bits
  were set, it would take 5 clock cycles.

however the fundamental "meaning" of mtcrf is, exactly as you describe
Alexandre, the numbering is contiguous and sequential.  whether *internally*
gcc treats it that way? i don't know.

basically i am talking us out of doing vertical CR Vector numbering

the downside of that is that even the most basic of augmentation to gcc will
require it to understand CR allocations for predicates.

which leaves us pretty much screwed *except* of course there is the c++ macro
idea that jacob came up with.

if Lauri really doesn't like c++ i am reasonably confident that something
similar involving macros could also be dreamed up.  it'll most likely look
absolutely dreadful but hey anyone who is a c programmer is used to that.

Alexandre just so you know i have asked if it is ok to reallocate one of the
cancelled RISCV budgets to gcc and binutils.  this is a decision not taken
lightly because it requires an unprecedented change to the MoU under which that
task was cancelled, and may result in questions from the external Audit team
that will need answering adequately.

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