[Libre-soc-bugs] [Bug 558] gcc SV intrinsics concept

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=558

--- Comment #46 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
appreciated the info jacob.  as a reminder: the purpose of this bigreport is
not for the solicitation of USD 250,000 and above to support the full required
feature set that will take 2 years to complete.

this is not happening: any efforts we make to focus on that and or depend on
that are guaranteed to jeapordise the entire project.

we specifically need somethimg that can be used for the next 8-12 months that
requires the absolute minimum work that, at just above assembly level provides
developers, unit test and HDL writers and more with the absolute bare minimum
needed to do their jobs.

if it gets thrown away in 8-12 months *we do not care*, it will have served its
purpose.

on that basis a *temporary* intrinsic representation of CR-mask-vectors, one
that is explicit and allows just-above-assembly to be explicitly written, fits
the reality of what we can get funding for, where full gcc support cannot.

fitting in with the CR register as a straight linear bitvector, if the
alternate CR mask intrinsic representation avoids the 1st 8 CRs it kinda
effectively becomes a separate regfile.  we *call* it "the same regfile" but
conceptually it is not.

in this way the fact that CR0-7 is seen as CR0.eq CR0.lt...  CR1.eq... where
the Vector versions are CR0.eq CR1.eq CR2.eq is irrelevant effectively and
resolved by the register allocator which requires a very weird modulo 4
bitlevel view of CRs.

at the point where the USD 250k funding needed for "full" gcc support is needed
including in the frontend all this can be reevaluated.

therefore the frontend is declared - aside from the explicit intrinsics -
completely out of scope.

right now - with some considerable urgency - we need to focus on what can be
achieved with 10-14 weeks work absolute max, around EUR 10-12k.

how can this be done?

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