[Libre-soc-bugs] [Bug 558] gcc SV intrinsics concept

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=558

--- Comment #43 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #41)
> (In reply to Jacob Lifshay from comment #40)

> > the cr logic ops and the cr from int and cr to int ops are generated
> > automatically by the instruction selector and by the register allocator.
> 
> this should be relatively easy since all you need to do is add the proper
> instructions for the generic register move ops generated by the register
> allocator:
> move bitvector from int to cr
> move bitvector from cr to int

if the CR masks are striped down all the eq bits, all the lt bits etc. this
meshes well.  the register allocator becomes a weird bitlevel allocator but
hey.

i would very much prefer that interactions between the cr mask intrinsics *not*
require tight integration and understanding in gcc other than in the regfile
allocator (keep gcc off the critical path)

that implies keeping *away* from CR0-7 as much as possible, so that use of a
crweird intrinsic doesn't completely destabilise scalar code.  once we have
bootstrapped up, got VC funding, this can be revisited.

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