[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #42 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #41)

> I have split the new issue FSM out from the issue/execute FSM, 

excellent that's a good incremental approach.

> and marked
> the places where the looping will be checked/done, and where PC/SRCSTEP will
> be updated. test_issuer.py and test_issuer_svp64.py are still happy.

superb.

i added that PowerDecoder.no_out_vec also needs to be checked (after execute)
i was going to refer you to the code where that's used in ISACaller but ha ha
i did it as this instead *sigh*

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/isa/caller.py;h=ccdbff1484797c070fc9c93f3165708f1acddf27;hb=HEAD#l1020

svp64_dest_vector needs to be replaced with using no_out_vec

i'm just going to move fetch_insn_o out so that the raw instruction is
dropped into pdecode permanently, see what happens.

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