[Libre-soc-bugs] [Bug 605] New: Extend ECP5_FPGA wiki page with JTAG testing/boot procedure for Libre-SOC test chip

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Feb 24 00:28:11 GMT 2021


            Bug ID: 605
           Summary: Extend ECP5_FPGA wiki page with JTAG testing/boot
                    procedure for Libre-SOC test chip
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: normal
          Priority: Normal
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: colepoirier at gmail.com
                CC: colepoirier at gmail.com,
                    libre-soc-bugs at lists.libre-soc.org
        Depends on: 517
            Blocks: 383
             Group: editcomments
          Deadline: 2021-03-10
   NLnet milestone: NLNet.2019.10.Wishbone
    parent task for 383
 budget allocation:

Once #517 JTAG STLINKv2 to FPGA connection guide wiki is complete:

* lckl to outline Libre-SOC test chip boot via jtag procedure for testing on
FPGA before the test ASIC is taped-out

*cole to make the wiki page and help with refining the JTAG process until lkcl
is satisfied that it is totally correct

*note* lkcl I set the due date to two weeks from the creation of this bug
report because it needs to be tested prior to the ASIC being taped out, which I
believe is sometime in march, please adjust the due date as you see fit

ecp5_fpga wiki url: https://libre-soc.org/HDL_workflow/ECP5_FPGA/

Precursor bug report currently in its final stages:

Bug #517 covers the creation and the wiki page that provides instructions on
the  the setup of STLINKv2 to FPGA wiring, ensuring their correctness so when
connected to power and used as as specified, the devices do not blow up and
release all the magic computer smoke they require to function.

SOC JTAG testing steps(?):
* Put processor into HALT
* Upload binary to address 0xXXXX via STLINKv2
* Profit?

Referenced Bugs:

[Bug 383] Complete first functional POWER9 Core
[Bug 517] Define JTAG pins and set up with litex for ulx3s85f
You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list