[Libre-soc-bugs] [Bug 600] Fix MSB0 issues in the SVP64 Assembler, Simulator and Decoder

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=600

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Comment on attachment 125
  --> https://bugs.libre-soc.org/attachment.cgi?id=125
suggested fixes for MSB0 issues in SVP64

23-i there.  otherwise looks good.

p.s. did i say i can't stand MSB0?

@@ -544,7 +544,7 @@ class SVP64Asm:
             svp64_prefix |= 0x1 << (31-9) # SVP64 marker 2
             rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
             for i, x in enumerate(rmfields):
-                svp64_prefix |= ((svp64_rm>>i)&0b1) << (31-x)
+                svp64_prefix |= ((svp64_rm>>(31-i))&0b1) << (31-x)

             # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
             yield ".long 0x%x" % svp64_prefix

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