[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Feb 14 14:10:34 GMT 2021


--- Comment #37 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 60e753c5b2f9ebe91557ca864dbff77c1559819c (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sun Feb 14 14:06:39 2021 +0000

    add indicator to PowerDecoder2 when no outputs are Vectorised

--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -1003,6 +1003,7 @@ class PowerDecode2(PowerDecodeSubset):
         self.in3_isvec = Signal(1, name="reg_c_isvec")
         self.o_isvec = Signal(1, name="reg_o_isvec")
         self.o2_isvec = Signal(1, name="reg_o2_isvec")
+        self.no_out_vec = Signal(1, name="no_out_vec") # no outputs are

Cesar this is the equivalent of svp64_dest_vector in ISACaller:


it can be used to detect that the 0..VL-1 loop should be ended early (scalar
dest). later when predication is added, the loop still continues and the
end-early test only triggers when the dest predicate bit is "1", even on scalar

(that's how we do VINSERT).

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