[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 7539c4c4b9e76b42b3447d13b8195bafec6cec17 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Thu Feb 11 15:57:25 2021 +0000

    comments in TestIssuer for SVP64PrefixDecoder

Cesar i have added in some TODO comments and the SVP64PrefixDecoder

@@ -22,7 +22,7 @@ from nmigen.cli import main
 import sys

 from soc.decoder.power_decoder import create_pdecode
-from soc.decoder.power_decoder2 import PowerDecode2
+from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
 from soc.decoder.decode2execute1 import Data
 from soc.experiment.testmem import TestMemory # test only for instructions
@@ -88,6 +88,7 @@ class TestIssuerInternal(Elaboratable):
         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT)
         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
                                      opkls=IssuerDecode2ToOperand)
+        self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix

         # Test Instruction memory
         self.imem = ConfigFetchUnit(pspec).fu


SVP64PrefixDecoder should be used combinatorially, it is very basic (5 lines),
to detect the presence of an SVP64 prefix.

if "yes" then the sv_rm field recorded (sync to register) and read another 32
bits insn stream

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