[Libre-soc-bugs] [Bug 591] New: Create yosys external cell wrapper for use by coriolis - DFF-SRAM block and Staf-SRAM blocks

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=591

            Bug ID: 591
           Summary: Create yosys external cell wrapper for use by coriolis
                    - DFF-SRAM block and Staf-SRAM blocks
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: normal
          Priority: High
         Component: Hardware Layout
          Assignee: colepoirier at gmail.com
          Reporter: colepoirier at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org, lkcl at lkcl.net
            Blocks: 383, 502
             Group: editcomments
          Deadline: 2021-02-12
   NLnet milestone: NLNet.2019.Coriolis2
    parent task for 383
 budget allocation:

Two yosys 'custom technology cell map' files/scripts need to be created of 1) a
512 Byte yosys generated DFF SRAM, so it can be used properly by the coriolis
workflow 2) Staf's SRAM block as an opaque VHDL simulation model (specifying
only inputs/outputs/ports) so that it can be used by lkcl and others not under
NDA to test soclayout/experiment12 and future soclayout work.

I have set the deadline for this bug as Friday 12 FEB 2021 because lkcl
communicated to me that this will become a blocker shortly, once a certain part
of JP's work has been completed.

"Cole: I think this stackoverflow question and answer may provide the process
needed to do this:
https://stackoverflow.com/questions/60143268/how-to-create-a-custom-technology-cell-map-for-yosys":
https://bugs.libre-soc.org/show_bug.cgi?id=502#c15

Note that Dave Shah has commented on the answer so it seems like it's the right
process."

"Staf: As asked in
http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001451.html
below is a generic SRAM simulation model in VHDL. I had to adapt the model for
multiple WE bits so the model is not fully tested. It does analyze with ghdl
though...": https://bugs.libre-soc.org/show_bug.cgi?id=502#c8

"Staf: I propose to use Verilog files to define blackboxes for yosys. This
would as follows for the SRAM bock...":
https://bugs.libre-soc.org/show_bug.cgi?id=502#c17


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=383
[Bug 383] Complete first functional POWER9 Core
https://bugs.libre-soc.org/show_bug.cgi?id=502
[Bug 502] determine SRAM block size and implement it
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