[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #22 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Cesar Strauss from comment #17)
> (In reply to Luke Kenneth Casson Leighton from comment #16)
> > Cesar would you like to plan / draw out a FSM which splits TestIssuer into
> > 2 FSMs?
> 
> Sure, I'm on it.

It works!

No regressions that I could see.

I had to add a register between instruction memory and decode, but I think it's
a good thing, despite taking an extra cycle.

-- 
You are receiving this mail because:
You are on the CC list for the bug.