[Libre-soc-bugs] [Bug 589] New: gigabit router asic

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=589

            Bug ID: 589
           Summary: gigabit router asic
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Milestones
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

placeholder.

* Porting PDKMaster to Sky130, including flow, simulations setup, design rules,
...: 3500EUR. Could be split in half with Cole
* Std. cell library optimization, more area efficiency + timing investigation:
1000EUR
* IO library: 125MHz operation + multiplexing capability in test chip for
ULPI/RGMII: 2500EUR
* flexram SRAM on Sky130, two options
  * single block: 750EUR
  * compiler that can generate different blocks: 1500EUR



We need to first define what one actually want to test and who does what.
Test only functional through JTAG patterns provided to me or full test on
ethernet and USB functionality ?
Will there be PCB needed with ethernet PHY and/or USB PHY ?
So budget needed may go from 1000EUR to 5000EUR I would say.

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