[Libre-soc-bugs] [Bug 550] binutils support needed for svp64

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=550

--- Comment #41 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to dmitry.selyutin from comment #40)
> Split the routine into parts so that it's clearer what's going on. An hour
> is lost trying to understand why gas doesn't understand
> `sv.setb/dm=r3/sm=1<<r3 5, 7`; turns out I must've used `-mpower9` switch...

oo sorry :)  yyeah, setb is probably a v3.0 instruction... yyep,
see v3.0B p1225 "p122 setb v3.0 Set Boolean"

> Now on my way to considering is_ldst and is_bc.

yyeah basically there, there are different SVP64 "mode" tables for:

* LD/ST instructions
* Branch instructions
* Condition instructions
* everything-else instructions ("normal")

(i haven't put Condition instruction mode-format into sv/trans/svp64.py yet)

see mode section:

https://libre-soc.org/openpower/sv/svp64/

which shows these pages:

* https://libre-soc.org/openpower/sv/cr_ops/
* https://libre-soc.org/openpower/sv/ldst/
* https://libre-soc.org/openpower/sv/branch/
* https://libre-soc.org/openpower/sv/normal/

and you can see the different specialist tables giving alternative
interpretations for the "Mode" bits

watch out for CR and Branch ops because actually some of the
*OTHER* fields (elwidth for example) are used as additional
mode bits (because of running out of space)

i do apologise that all the bits in the specs are in MSB0 order.
if you take enough drugs you either melt your brain enough to
follow along or, more likely, don't care one way or the other.

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