[Libre-soc-bugs] [Bug 50] nmigen pinmux

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=50

--- Comment #78 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
(In reply to Luke Kenneth Casson Leighton from comment #77)
> (In reply to Andrey Miroshnikov from comment #76)
>   42 # JTAG boundary scan reg addresses
>   43 BS_EXTEST = 0
>   44 BS_INTEST = 0
>   45 BS_SAMPLE = 2
>   46 BS_PRELOAD = 2
After some experimentation, and discussion here:
https://libre-soc.org/irclog/%23libre-soc.2021-12-11.log.html

figured out the main test modes:
-BS_SAMPLE: core/pad are connected together, the TDI data has no effect on the
peripherals. In this case JTAG is ONLY used for *sampling* the state of the I/O
connected the JTAG's shift register.
EX_TEST/IN_TEST: core/pad connections are broken, JTAG has full control over
the state of core inputs and pad outputs. In this case the TDI data has to be
tailored to the desired test. At the same time TDO returns the JTAG shift
register data.

> 
> generally, having magic constants for addresses is frowned on.
Indeed, but we'll probably have to bare with them in c4m-jtag for now.

> 
> ok, a *Software Engineer* looks on magic constants with either horror
> or irritation. sometimes amusement.
:')

> awwwesome.  quite an amazing feeling, isn't it?
Very much so!

> do make sure to use the names because i've realised over the past couple
> of days that create_resources() has to merge with create_pinouts().
> long story, will explain on IRC.
Yes, this is still in progress, I'll be implementing it once I get back.

So far there are four test cases within the jtag test:
-Before the peripherals are exercised:
1. Send 0xFFFFF via TDI in EX_TEST mode
2. Send 0xFFFFF via TDO in BS_SAMPLE mode
-After peripherals tested (all pad inputs and core outputs remain asserted)
3. Send 0x00000 via TDI in EX_TEST mode
4. Send 0x00000 via TDI in BS_SAMPLE mode

The expected results are:
1. All core outputs and pad inputs should be low. All core inputs and core
outputs should be high (as these come from JTAG).
2. All signals should be low (as JTAG TDI is ignored, and nothing has been
asserted yet).
3. All pad inputs and core output enables should remain asserted. Core output's
and pad input's low.
4. All signals should be high.

Asserts have not been added, but I started writing some code (commented out),
which will test outputs/inputs by detecting '__o' or '__i' in the string of the
signal name.

Latest commit:
https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/testing_stage1.py;h=c05ed5e6e82784d6a9d4cfe1ace24f39c0fec984;hb=8026e22d89673d81d463d9faea54a76f76522c47#l653

Things I haven't considered:
-JTAG register retains data given by TDI, so should be cleared before each test
case. Leaving it in may affect the system when switching to EX_TEST mode.
-Some of the combinatorial logic added in GPIOs/I2C/UART will need to be moved
to dedicated tests, so that JTAG can fully control all signals.

For now I will take a backseat (pardon the pun), as I will be getting ready for
my driving test. 21st onwards I'll return to work full time again.
During the next week and a half I'll probably jot things down or do simple
clean up (work that doesn't require too much thinking).

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