[Libre-soc-bugs] [Bug 745] OP_TERNLOG instruction

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=745

--- Comment #38 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
    result <- [0] * XLEN
    idx <- [0] * 3
    do i = 0 to XLEN - 1
      idx[0] <- (RT)[i]
      idx[1] <- (RA)[i]
      idx[2] <- (RB)[i]
      result[i] <- (TLI & ROTL64(1, idx)) != 0

the style in the Power ISA is to use less lines, and that's possible
here with:

    do i = 0 to XLEN - 1
      idx <- (RT)[i] || (RA)[i] || (RB)[i]
      result[i] <- (TLI & ROTL64(1, idx)) != 0

also, using ROTL64 seems overkill (and is supposed to be for shiftrot)

i suspect this will do:

    do i = 0 to XLEN - 1
      idx <- (RT)[i] || (RA)[i] || (RB)[i]
      result[i] <- TLI[idx]

don't be tempted to substitute idx there, the parser won't be able
to cope because it can't identify the size of idx.  if those 3 lines
don't work, then this should "fix" that: pre-declaring idx to a known
size.

    idx <- [0] * 3
    do i = 0 to XLEN - 1
      idx <- (RT)[i] || (RA)[i] || (RB)[i]
      result[i] <- TLI[idx]

no i don't want the parser to turn into a 2-pass Monster right now.

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