[Libre-soc-bugs] [Bug 753] simulator somehow ends up with SO set even though nothing writes to it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=753

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)

> Ok, when we have time, we should separate Rc decoding from overflow decoding
> in the CSVs.

they're separated (different columns), it's the heavy interdependence
(OE cannot exist without Rc due to XER.SO *also writing to CR0) that
is the problem, and that's basically unfixable: it's *by design* as
part of the ISA. annoying as that may be.

> > this tends to suggest that disallowing Rc=1 for ternlog is probably a good
> > idea [and would free up more bits]
> 
> Yes, I'm also biased against ternlogi having Rc anyway, though not for any
> reason I can express at the moment, hence why I haven't mentioned it
> before...

i think, arithmetically, it has no meaning. CR0.EQ to zero, sure, but CR0.LT?
or CR0.SO? they make no sense, because this is a "Logical" operation, and there
are no Rc=1 Logical Power ISA operations (and then the bit is unused, sigh)

> I'll remove "ternlogi." and just have "ternlogi".

excellent.

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