[Libre-soc-bugs] [Bug 753] simulator somehow ends up with SO set even though nothing writes to it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=753

--- Comment #4 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
>   1 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry
> in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl
> pipe,comment,form,CONDITIONS,unofficial,comment2
>    2
> --------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,
> 0,0,0,RC,0,0,ternlogi,TLI,,1,unofficial until submitted and
> approved/renumbered by the opf isa wg
> 
> "RC=1" is a request to PowerDecoder2 to decode both OE and Rc flags,
> which will then (sigh) decode those bits manually (a hangover from
> using microwatt decode1.vhdl and decode2.vhdl)

Ok, when we have time, we should separate Rc decoding from overflow decoding in
the CSVs.

> this tends to suggest that disallowing Rc=1 for ternlog is probably a good
> idea [and would free up more bits]

Yes, I'm also biased against ternlogi having Rc anyway, though not for any
reason I can express at the moment, hence why I haven't mentioned it before...

I'll remove "ternlogi." and just have "ternlogi".

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