[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=485

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|colepoirier at gmail.com       |lkcl at lkcl.net

--- Comment #86 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
TODO: adapt to Minerva FetchUnitInterface

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/minerva/units/fetch.py;hb=HEAD

  23         # inputs: address to fetch PC, and valid/stall signalling
  24         self.a_pc_i = Signal(self.addr_wid)
  25         self.a_stall_i = Signal()
  26         self.a_i_valid = Signal()
  27         self.f_stall_i = Signal()
  28         self.f_i_valid = Signal()
  29 
  30         # outputs: instruction (or error), and busy indicators
  31         self.a_busy_o = Signal()
  32         self.f_busy_o = Signal()
  33         self.f_instr_o = Signal(self.data_wid)
  34         self.f_fetch_err_o = Signal()
  35         self.f_badaddr_o = Signal(bad_wid)

aldo contains stall in and out

  31 class Fetch1ToICacheType(RecordObject):
  32     def __init__(self, name=None):
  33         super().__init__(name=name)
  34         self.req           = Signal()
  35         self.virt_mode     = Signal()
  36         self.priv_mode     = Signal()
  37         self.stop_mark     = Signal()
  38         self.sequential    = Signal()
  39         self.nia           = Signal(64)
  40 
  41 
  42 class ICacheToDecode1Type(RecordObject):
  43     def __init__(self, name=None):
  44         super().__init__(name=name)
  45         self.valid         = Signal()
  46         self.stop_mark     = Signal()
  47         self.fetch_failed  = Signal()
  48         self.nia           = Signal(64)
  49         self.insn          = Signal(32)

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