[Libre-soc-bugs] [Bug 745] OP_TERNARY instruction

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=745

--- Comment #32 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #30)
> I added the ternlogi spec pseudo-code.
> 
> While I'm at it, I become annoyed with constantly having -.csv 

erm...

> and sv_decode.vhdl 

that one should be .gitignored

> be untracked files in openpower/isatables/
> Should I add them to .gitignore or should I commit them?

ermmm...ermermerm....  these are actually important to have
properly examined, lwzu for example is clearly a mistake.
can you please raise a bugreport about them, to be investigated
in the meantime i'll put something in sv_analysis.py

insn,CONDITIONS,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
dcbz,,0,EXTRA2,0,0,0,0,RA_OR_ZERO,RB,0,0,0,0,0
lwzu,SVP64BREV,0,EXTRA2,0,0,0,0,RA_OR_ZERO,0,RC,RT,0,0,RA
lbzu,SVP64BREV,0,EXTRA2,0,0,0,0,RA_OR_ZERO,0,RC,RT,0,0,RA
lhzu,SVP64BREV,0,EXTRA2,0,0,0,0,RA_OR_ZERO,0,RC,RT,0,0,RA
lhau,SVP64BREV,0,EXTRA2,0,0,0,0,RA_OR_ZERO,0,RC,RT,0,0,RA
lfsu,SVP64BREV,0,EXTRA2,0,0,0,0,RA,0,RC,FRT,0,0,RA
lfdu,SVP64BREV,0,EXTRA2,0,0,0,0,RA,0,RC,FRT,0,0,RA
1/6=mtfsb1,,0,EXTRA2,0,0,0,0,0,0,0,0,0,CR1,0
2/0=mcrfs,,0,EXTRA2,0,0,0,0,0,0,0,0,0,BF,0
2/6=mtfsb0,,0,EXTRA2,0,0,0,0,0,0,0,0,0,CR1,0
4/6=mtfsfi,,0,EXTRA2,0,0,0,0,0,0,0,0,0,CR1,0

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