[Libre-soc-bugs] [Bug 50] nmigen pinmux

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=50

--- Comment #73 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Andrey Miroshnikov from comment #72)
> (In reply to Luke Kenneth Casson Leighton from comment #71)
> > (In reply to andrey from comment #70)
> > +    print ("bs pad keys", top.jtag.boundary_scan_pads.keys())
> Thanks for the fix. I'll be sure to use .keys() from now on, I was trying to
> figure out how to view the dictionary keys too...
> 
> > flipping the boundary scan bits, as is done in test_jtag_tap_srv.py
> Started working on this. The sequence so far is:
> https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/testing_stage1.py;
> h=03c8c5def0a034e4f2657d791f5d9e8239625f17;
> hb=dd0c84a11f93661d1682a95419dcf04aa91cad96#642
> (Edit: apologies, forgot to update link)
> 1. Reset the JTAG BS by doing:
> yield from jtag_set_reset(top.jtag)
> 2. Manipulate the core and pad signals (for example GPIO 0):
> top.jtag.ios['gpio_0__gpio0__i'].core.i.eq(1)
> top.jtag.ios['gpio_0__gpio0__i'].pad.i.eq(0)
> 3. Call an empty yield to progress to next clock cycle.
> 
> You mentioned that Tck is toggled by jtag_set_reset(), and I checked this is
> the case in the code:
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtagutils.py;
> hb=0eb75ea62a5f20e1824f9a25daefda9ff0340e53#l23
> 
> I looked at the test_jtag_tap_srv.py as a basis, and I don't see anything
> done other than the steps I mentioned. I'm ignoring the jtag_read_write_reg
> however, as I don't expect it to be needed for this task yet.
> 
> ...
> UPDATE
> ...
> 
> As I was writing this, I spotted that I missed "yield from" when using
> "jtag_set_reset()", so that's one issue solved.
> 
> However I get an AttributeError because inside "tms_state_set()", the code
> is trying to access "cbus" object to toggle Tck:
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtagutils.py;
> hb=0eb75ea62a5f20e1824f9a25daefda9ff0340e53#l25
> yield dut.cbus.tms.eq(bit)

use test_jtag_tap.py instead.

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/test_jtag_tap.py;h=757c313c54a67db054097cc8dba979cac64424b1;hb=0eb75ea62a5f20e1824f9a25daefda9ff0340e53

> Our Blinker top.jtag does NOT have cbus. Should it have one?

no.  look at c4m-jtag tap.py

https://git.libre-soc.org/?p=c4m-jtag.git;a=blob;f=c4m/nmigen/jtag/tap.py;h=1f3d424cbd7451c0434e0c71168f5aa0935af860;hb=c2bf4810f9f91ced7fcda777b92b86ab353da288#l328

always hunt down the inheritance tree, either in a browser window
or keep the source code open in a terminal.

$ ps auxww | grep vi | wc
    586    7162   56392

for the past 10 years i now have to do "jobs | grep {filename}"
in many of the xterms i have open.

> And if so, what is it for?

https://git.libre-soc.org/?p=c4m-jtag.git;a=blob;f=c4m/nmigen/jtag/bus.py;h=d1532bc08d0d8170c5b7c5e62dba67f8c6fe709a;hb=c2bf4810f9f91ced7fcda777b92b86ab353da288#l18

  18 class Interface(Record):
  28         layout = [
  29             ("tck", 1, Direction.NONE),
  30             ("tms", 1, Direction.NONE),
  31             ("tdo", 1, Direction.FANOUT),
  32             ("tdi", 1, Direction.FANIN),
  33         ]

-- 
You are receiving this mail because:
You are on the CC list for the bug.