[Libre-soc-bugs] [Bug 724] Determine required memory compiler developments

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=724

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Staf I identified another location of SRAMs: the DCache and ICaches.
there are two types:

* TLB and Page Table Entry caches
  - 1R1W
  - read on next cycle (sync)
  - write updates on NEXT cycle (sync)
  - forwarding needed (can be done externally,
    not part of SRAM)
  - 64 rows
  - 128 bit for tags, and 92 bit for PTEs
  - 4 write-enables therefore 4x32-bit for tags
    and 4x23-bit for PTEs

you can see the code which reads, modifies, then writes back
some bits.  I will make this use a Memory so it is more obvious

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/dcache.py;h=d0829f4df8ac56dbcf96b5b018a66730e24261c4;hb=1cf999d43c244b49894d77e8f2151089496239eb#l432

about 1k in size, each there, QTY 4 to be used.  i will check
that ICache is the same spec (should be)

* Cache SRAM
  - 1R1W
  - 128 rows
  - 64 bits
  - entire row written (no multiple wens)
  - read and write both 1 clock cycle

each 1k in size (128x8), QTY 8 to be used.

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/cache_ram.py;h=50ee1367cc84301bcf9cecf0f6cae51d13273227;hb=1cf999d43c244b49894d77e8f2151089496239eb

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