[Libre-soc-bugs] [Bug 751] idea for reducing dependency matrixes in 6600-derived architecture with register renaming

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=751

--- Comment #10 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #8)
> [that's five output registers, not two]

yeah, yeah...i don't want to type 5 registers. also, not all ALUs that can add
necessarily must support all possible add-like instructions, they may just
support add[i][.] and nothing else, so rt and cr0 would be sufficient there.

> this creates false (unnecessary) dependencies that in turn puts pressure
> on the read/write ports of the regfile and/or on the number of FUs required
> to hold in-flight data due to missed write opportunities.

well...there is always exactly one write port on the register, cuz the register
is only ever written by its corresponding ALU. whenever an instruction is
finished executing, it always immediately writes its result to the
corresponding register, there are never any reasons to delay at all, once
execution has started, so...there are never missed write opportunities.

re: unnecessary dependencies: other than load-update (which is weird and could
be split in 2 uops: addr calc and load), basically all instructions can/should
write all outputs simultaneously (when they finish the last stage of their
execution pipe), so we never really have the case where some instructions' cr0
output is ready 5 cycles earlier than its rt output.

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