[Libre-soc-bugs] [Bug 745] OP_TERNARY instruction

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=745

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #21)
> (In reply to Luke Kenneth Casson Leighton from comment #20)
> > (In reply to Jacob Lifshay from comment #19)
> >  
> > > Yeah, I can switch back, though FHDLTestCase has some serious shortcomings,
> >
> > then you should have fixed it!
> 
> Ok, I fixed it and switched the tests to use the newly-fixed FHDLTestCase.

brilliant.

> I also moved ternlogi to the shiftrot pipe 

great.  really, a compile-time option needs adding which can disable
it.  added to pspec.

  22     def __init__(self, pspec):
  22.5       self.draft_bitmanip = hasattr(pspec, "draft_bitmanip")
                       and psec.draftbitmanip == True
  23         super().__init__(pspec, "main")

  92.5       if self.draft_bitmanip:
  93             with m.Case(MicrOp.OP_TERNLOG):
  94                 # TODO: this only works for ternaryi, change to get lut
value

that has the advantage of identifying draft instructions as well as
making it abundantly clear that they are, in fact, draft (unofficial)

see test_core.py as to how to set them up:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_core.py;h=a35545024e23ba05a8ad71ac96e2500e0c5b4612;hb=75bdc1747f32a4fb6cf848ed8b5c68ef2f683f4c#l245

the new option draft_bitmanip=True will need to be added



btw, this move should not have been left uncommented in the commit message:
it has nothing to do with ternlogi.

it should have been done as a completely separate commit,
"moving rotator module connectivity)

actually, please put that back so to line 102, back associated with
the Cat() because it now looks like the Cat statement has no comment
or explanation associated with it.

 102         comb += Cat(rotator.right_shift,
 103                     rotator.clear_left,

@@ -65,6 +71,10 @@ class ShiftRotMainStage(PipeModBase):

         comb += o.ok.eq(1)  # defaults to enabled

+        # outputs from the microwatt rotator module
+        comb += [o.data.eq(rotator.result_o),
+                 self.o.xer_ca.data.eq(Repl(rotator.carry_out_o, 2))]
+
         # instruction rotate type
         mode = Signal(4, reset_less=T


> and removed the now-redundant
> bitmanip pipe, I still need to add the fu unit test.

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