[Libre-soc-bugs] [Bug 671] convert spec pseudocode to use XLEN width

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Aug 30 20:17:41 BST 2021


--- Comment #48 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to dmitry.selyutin from comment #46)

> The confusion is raised by these words from the spec:
>     A count of the number of one bits in each word of regis-
>     ter RS is placed into the corresponding word of register
>     RA. This number ranges from 0 to 32, inclusive.
> I assumed "word" implies 32-bit. However, I think your rationale fits
> better. Let me re-check these.

with elwidth overrides we are wandering into a partiticularly important
strategic part of SVP64, which is *not* approved yet by the OPF ISA WG
and will need to be submitted via an official process.

what we are doing - right now - is actually *defining* how SVP64 shall
fit on top of these Power ISA scalar v3 0B operations.

i.e. it is *not* up to the creators of the Power ISA v3.0B
to say how the combination of Draft SVP64 shall behave: that is down
to us.

thus it is a slightly weird situation in which we have to think,
"64 bit versions of these instructions, must be v3.0B compliant
without a shadow of doubt, but 32 16 and 8 bit versions,
those are our responsibility to think through and define...
... oh and then submit to the OPF ISA WG when they are ready"

consequently, the actual wording of the v3.0B scalar spec is *not*
helpful for defining what shall happen at 32, 16, or 8 bit: it is
only strictly helpful at the full 64 bit

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