[Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=617

--- Comment #14 from Cesar Strauss <cestrauss at gmail.com> ---
INT and CR predication work! (without zeroing mode)
All current predication tests pass!

DONE:
* new FSM for predicate fetch
* INT predicate fetch
* add src/dest step VL-loop on Issue FSM, skipping consecutive zeros in the
mask
* synchronize TestIssuer and ISACaller on vector ops
* CR predicate fetch
* shifting-out skipped masks bits for both CR and INT pred, for reentrancy
* a few MSB0 fixes along the way

TODO:
* Zeroing single
* Zeroing twin

-- 
You are receiving this mail because:
You are on the CC list for the bug.