[Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Apr 25 21:28:51 BST 2021


--- Comment #14 from Cesar Strauss <cestrauss at gmail.com> ---
INT and CR predication work! (without zeroing mode)
All current predication tests pass!

* new FSM for predicate fetch
* INT predicate fetch
* add src/dest step VL-loop on Issue FSM, skipping consecutive zeros in the
* synchronize TestIssuer and ISACaller on vector ops
* CR predicate fetch
* shifting-out skipped masks bits for both CR and INT pred, for reentrancy
* a few MSB0 fixes along the way

* Zeroing single
* Zeroing twin

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