[Libre-soc-bugs] [Bug 393] Hook up augmented-Wishbone Memory Bus to LDSTCompUnit (via PortInterface)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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       The table of|"lkcl"={amount:300,         |"lkcl"={amount=300,
  payments (in EUR)|paid=2020-08-21}            |paid=2020-08-21}
     for this task;|                            |
        TOML format|                            |

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