[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Apr 20 13:20:07 BST 2021


--- Comment #32 from Staf Verhaegen <staf at fibraservi.eu> ---
Created attachment 131
  --> https://bugs.libre-soc.org/attachment.cgi?id=131&action=edit
SRAM block spice simulation

Here are the results of the verification I did on the SRAM block.  I simulate
four clock cycles:
- cycle 1: Write 0 to address 0
- cycle 2: Write $FFFFFFFFFFFFFFFF to address 5
- cycle 3: Read address 0
- cycle 4: Read address 5

In the picture you can see the clk, d (=data_in) and we (=write-enable) signals
on the top graph and clk and q (=data_out) on the bottom one.
You can see the write through of written data in first 2 cycles and correct
values read in the next two cycles.

Also the clk->q delay is shown in the graph for typical corner. A value of
almost 2ns is seen. This is without parasitics so with that included I think
the clk->q will be more like 3-4ns meaning 200MHz is I think not a problem. All
depends of course how much logic is after the SRAM.

Unfortunately I had to use the proprietary Eldo spice simulator as ngspice did
not find a DC solution after two days of simulation. Xyce could not read the
TSMC SPICE models although that should be possible with some helper tools. The
Eldo simulation finished in about 15 minutes.

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