[Libre-soc-bugs] [Bug 204] Transition from symbolic to real Cell Library for 180nm layout

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=204

--- Comment #7 from Staf Verhaegen <staf at fibraservi.eu> ---
So to summarize. For the single core tape-out the transition from symbolic to
real layout has been done. I have a library release for TSMC 0.18um, this
contains fab data that is under NDA so can not be made public.

To allow people in the public the redo the full flow with everything open the
FreePDK45 PDKMaster release has been set up to do a real flow on the libreSOC
prototype. It show the full flow to all people participating in the flow:

* First there is a description of the technology in a PDKMaster source file:
https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45/-/blob/master/c4m/pdk/freepdk45/pdkmaster.py
* This technology setup file is used by c4m-flexcell to generate a standard
cell library using PDKMaster:
https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45/-/blob/master/c4m/pdk/freepdk45/flexlib_.py
* Both the technology setup and the flexcell standard cell library are then
exported to Coriolis python code:
https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45/-/blob/master/scripts/export_coriolis.py
* Finally this Coriolis setup in then used in a Coriolis flow to do synthesis
and place and route:
https://git.libre-soc.org/?p=soclayout.git;a=blob;f=experiments9/freepdk_c4m45/coriolis2/settings.py;h=cc10a52e3b3968b41ae7b630624b0a6f5ed14398;hb=HEAD

To run the FreePDK45 P&R yourself you don't need to redo these things yourself. 
* Setup up libre-soc development environment + Coriolis environment
* Check out soclayout (
* Then you can run the flow with ./build_full.sh in either
experiments9/freepdk_c4m45 (long) or experiments10_verilog/freepdk_c4m45
(faster). It currently still fails with an error in BigVia._doCutMatrix.

I think this fulfills the requirement of this bug.

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