[Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Thu Apr 15 23:58:24 BST 2021
https://bugs.libre-soc.org/show_bug.cgi?id=604
--- Comment #33 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
440 # mbits := unsigned('0' & data(4 downto 0));
441 mbits = selectconcat(SelectableInt(0,1), data[58:63])
442 assert(mbits.bits==6) #variable mbits : unsigned(5 downto 0);
this is incorrect. the conversion is as follows:
* x downto y converts to 63-x downto 63-y
* 4 downto 0 is therefore 59 downto 63
however python lists are to the end plus 1
therefore 5 downto 0 is data[59:64]
NOT
58:63
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