[Libre-soc-bugs] [Bug 620] post-layout simulation needed using cocotb

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=620

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
slightly messy however it is functional:

https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=blob;f=ls180/post_pnr/cocotb/test_add_boundary.py;h=b518224664cd7c2ad4a2e2672aa05aac3a012a59;hb=HEAD#l177

this test uses experiments10_verilog post-P&R vst files (*cts*), running a JTAG
boundary scan.

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