[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #124 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #122)
> ## Images of wires on FPGA and on ft232r
> 
> which FPGA?

Fixed and added a note that there will be new images for the versa ecp5, once
you are able to do them.

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