[Libre-soc-bugs] [Bug 620] post-layout simulation needed using cocotb

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=620

--- Comment #7 from Staf Verhaegen <staf at fibraservi.eu> ---
I seem to have success in iverilog with the following code:

> `timescale 1ns/1ps
> 
> module clkdrv(output reg clk);
> 
> initial begin
>     clk = 0;
>     forever begin
>         #10 clk = ~clk;
>     end
> end
> 
> endmodule

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