[Libre-soc-bugs] [Bug 620] post-layout simulation needed using cocotb

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Apr 8 00:44:19 BST 2021


--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---





i believe it should be extremely straightforward to combine the above, this is
not nmigen just cxxrtl from yosys, to create a jtag tester which speaks openocd
"jtagremote" socket protocol.

at that point it will be possible to connect directly to the simulation with
.svf files, from openocd commandline, as if it was a real ASIC or FPGA.

with cxxsim or more to the point yosys having both verilog and ghdl it should
be possible to do pre and post pnr simulation.

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