[Libre-soc-bugs] [Bug 620] post-layout simulation needed using cocotb

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=620

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

https://tomverbeure.github.io/2020/11/04/VHDL_Verilog_Cosimulation_with_CXXRTL.html


https://github.com/tomverbeure/cxxrtl_eval/blob/master/blink_basic/main.cpp

https://git.libre-soc.org/?p=litex.git;a=blob;f=litex/build/sim/core/modules/jtagremote/jtagremote.c;h=87c7c159842231bba2c5e94e1e054f71c5d90e36;hb=35929c0f8a8f1cc098a6b6ebb569caca8df8c08d

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/test_jtag_tap.py;hb=HEAD

i believe it should be extremely straightforward to combine the above, this is
not nmigen just cxxrtl from yosys, to create a jtag tester which speaks openocd
"jtagremote" socket protocol.

at that point it will be possible to connect directly to the simulation with
.svf files, from openocd commandline, as if it was a real ASIC or FPGA.

with cxxsim or more to the point yosys having both verilog and ghdl it should
be possible to do pre and post pnr simulation.

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