[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #91 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
rrright.

i hacked openocd into submission, on the hla transport.  anything that
assumed a target existed - OUT.  anything that caused failures due to
assumptions that a target existed - OUT.

as a direct result of this i was able to get to the same status as the
dapdirect_jtag .cfg file, i.e. reproduce this exact same error:

Debug: 83 5 stlink_usb.c:1019 stlink_usb_error_check(): unknown/unexpected
STLINK status code 0x5

at which point, the next error line reported was:

Error: 84 5 stlink_usb.c:3493 stlink_open(): init mode failed (unable to
connect to the target)

which tells us that it *might* actually be the case that communication
is in fact being attempted with the ECP5 over the JTAG lines.

whether that's working or not is a different matter.

the speed options here are pretty damn high - 140 khz is the bare minimum
and i suspect that's simply too noisy / fast

i have ordered a Waveshare USB Blaster and will see if that does any better.
the other option is an FT232 of some description and define some arbitrary
pin-mappings to bit-bang as JTAG.

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