[Libre-soc-bugs] [Bug 202] potential changes to LibreSOC HDL to suit coriolis2

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=202

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
verilog and ilang respect cases on names, where vhdl does not.  this is causing
issues on cosimulation but also name clashes in the P&R.

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