[Libre-soc-bugs] [Bug 526] create dry-run 180nm GDS-II files for IMEC

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Nov 30 14:21:28 GMT 2020


--- Comment #69 from Jean-Paul.Chaput at lip6.fr ---

> > So I've successfully done the P&R with Staf FlexLib & I/O pads. I will
> > commit that work under experiments11. Only I or Staf will be able to
> > run it because it needs the NDA (this directory, however, will not
> > contains any classified information).
> sigh.  now we have two sets of identical work to maintain.  so, when i add
> the core back in, you have to duplicate that.

  Yes that's far from ideal. However, just copying the ".il" generated by
  nMignen should suffice. And afterward we run the automated P&R.

> > * Could it be possible for the JSON file to be human-readable formatted?
> with some independent parser tool, probably yes.  unix philosophy applies.

  With Python/JSON this is very easy... Already did.

> >   It will not induce significant slowdown and I will be able to perform
> >   manual tweaks more easily.
> mmm... if you're doing manual tweaks to an auto-generated
> (machine-generated) file this raises alarm bells in my mind.

   And I totally agree. I mean, it is useful for debugging purpose.
   If I can read the JSON I can quickly pinpoint the problem, make
   a manual correction to see if it works, then suggest/request an
   appropriate fix (fast debug loop).

> > * In your json file, you seems to have inverted vdd/vss on the I/O pads.
> >   "vdd" should be connecteds to "power" and "vss" to "ground".
> ah ok good catch.

  Benefit of human readable file...

> > * The power pads are too far off the side, at least put one ordinary pad
> >   at the very begin/end of each side.
> again, to remind you: https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/29
> this is exactly what i fixed and dealt with as part of the
> "pads.useChipSize" parameter.
> by using the core size not the chip size then regardless of the chip size
> the positions of the IOpads align up perfectly with the core.

  Yes, I didn't forgot. But it means that we loose some space at the end of
  each side. If we are core limited, no problem. If we are pad limited, this
  may be bad (especially if the core is *much* smaller than the corona).
  Anyway, for a better power distribution it is likely that I will change
  the whole approach.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list