[Libre-soc-bugs] [Bug 526] create dry-run 180nm GDS-II files for IMEC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=526

--- Comment #67 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #64)
> Hello Luke,
> 
> I will investigate tomorrow your explanation. I've succeeded in getting
> it to work by re-cloning the repository.

honestly don't bother!  re-cloning is Bad(tm) but if it works, it works.


> So I've successfully done the P&R with Staf FlexLib & I/O pads. I will
> commit that work under experiments11. Only I or Staf will be able to
> run it because it needs the NDA (this directory, however, will not
> contains any classified information).

sigh.  now we have two sets of identical work to maintain.  so, when i add the
core back in, you have to duplicate that.


> The P&R works ok and it is DRC clean (with the golden tool Mentor/Calibre).

excellent.

> Some points:
> 
> * Could it be possible for the JSON file to be human-readable formatted?

with some independent parser tool, probably yes.  unix philosophy applies.

>   It will not induce significant slowdown and I will be able to perform
>   manual tweaks more easily.

mmm... if you're doing manual tweaks to an auto-generated (machine-generated)
file this raises alarm bells in my mind.


> * In your json file, you seems to have inverted vdd/vss on the I/O pads.
>   "vdd" should be connecteds to "power" and "vss" to "ground".

ah ok good catch.

> * The power pads are too far off the side, at least put one ordinary pad
>   at the very begin/end of each side.

again, to remind you: https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/29

this is exactly what i fixed and dealt with as part of the "pads.useChipSize"
parameter.

by using the core size not the chip size then regardless of the chip size
the positions of the IOpads align up perfectly with the core.

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