[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #94 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #92)

> All that said, I haven't done Karnaugh map minimizations for hardware
> purposes in a long time, and never such massive ones, so my intuitions may
> be way off.  I'd have to work it out more thoroughly to trust them ;-)

:)

whatever it is, it's an order of magnitude too large.  8-bit shifting
is inherently going to be 4x larger than anything that's involving 16-bit
shifting.  with the amount of in and outs, inherently it's going to be
too much.

this is the *decoder* phase we're referring to, here.  partial-decoded
instructions should normally be stored in 1R1W SRAMs with clean, clear
subdivisions: we're looking at 4R4W (which is insanely costly).

bottom line, 8-bit aligment of instructions is eliminated from consideration
(the 8-bit marker and using PC[0] as state).

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