[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Nov 29 04:45:58 GMT 2020


--- Comment #91 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Alexandre Oliva from comment #90)
> Another occurrence we may want to ponder whether to allow is a pair of
> adjacent 10-bit insns, the first of them saying the next insn is a 32-bit
> one.  Though a 10-bit insn can be encountered whenever a 32-bit insn is
> expected, tt makes very little sense, if my assumption is correct that every
> 10-bit insn can also be encoded as 16-bit.  We might get some
> simplifications (and opportunities for future extensions) by ruling such
> pairs (or long sequences) out.

I'd argue that two 10-bit instructions in a row should be legal, since there
could be a branch to the second 10-bit instruction like the following:

h.add r5, r3
h.add r5, r4
b loop

If we didn't allow 2 10-bit instructions in a row, we'd have to change 1 of
them to 32-bit or add a nop or something -- wasting space.

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