[Libre-soc-bugs] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #71 from Cesar Strauss <cestrauss at gmail.com> ---
I finished porting the DummyALU test case.

I found a bug in the test case itself. DummyALU is built with CompCROpSubset,
but the test case instanced a MultiCompUnit with CompALUOpSubset.

The next step is to add test cases for read and write masks, and shadow/go_die.

To see the current work:
$ python ~/src/soc/src/soc/experiment/test/test_compalu_multi.py 

# MultiCompUnit + FSM Shifter:
$ gtkwave test_compunit_fsm1.gtkw

# MultiCompUnit + ALU:
$ gtkwave test_compunit_regspec1.gtkw

# MultiCompUnit + DummyALU:
$ gtkwave test_compunit_regspec3.gtkw

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