[Libre-soc-bugs] [Bug 526] create dry-run 180nm GDS-II files for IMEC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=526

--- Comment #56 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Jean-Paul.Chaput from comment #54)
> (In reply to Staf Verhaegen from comment #53)
> > (In reply to Luke Kenneth Casson Leighton from comment #52)
> > > (In reply to Jean-Paul.Chaput from comment #51)
> > > 
> > > ok - can you add that to alliance-check-toolkit, and set up an example?
> > > (is there a Phantom version of FlexLib that's publicly available? i was
> > > under the impression that there would be!)
> > > 
> > > i'd very much prefer that we're "tracking" what you're doing (right up
> > > to the point where the "real" (NDA'd) version of FlexLib is used) and
> > > have full public replicability.
> 
>   I completely understand that. I *may* be able to provide an obfuscated
>   version of FlexLib which should not infringe the NDA. But, two problems:
> 
>   1. It would take a little time (to be 100% sure that nothing under NDA
>      is still present). And I am critically low on that.
> 
>   2. Even if [1] is fullfilled, Staf is against it at the moment, because
>      of potential FUD from the foundry. And he do not want to take any
>      action that could jeopardize his relationship with IMEC/Foundry.

I will indeed not provide the needed information from my upstream version of
FlexLib nor will I take reproducibility for non-NDA people into account during
further development of FlexLib.

I don't forbid users of FlexLib to distribute information for reproducibility
if they think they can do it without violating the NDA.

> > * second given the placement + layout of the cells in open PDK should allow
> > to verify that actual produced chip is the one that is taped by delidding an
> > decapsulating the chip.
> 
>   You mean to provide the placement done with *FlexLib+real foundry* ?

Yes, with coordinates in integer grid points not real dimension.

>   Because otherwise, the placements are likely to differ. And without the
>   wiring, how do you intend to check the layout correctness ?

You have the nets in the netlist and can trace back the connections on the
decapsulated chip. So you can verify the interconnect on the real chip with the
one in the netlist.
If the problem is that you don't trust the guy doing the P&R himself and want
to check him, you need to get NDA yourself.

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